LAN91C111 datasheet(37/125 Pages) MICROCHIP

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DS00002276A-page 37

LAN91C111

7.8

Reset

The chip (MAC & PHY) performs an internal system reset when either (1) the RESET pin is asserted high for at least

100ns, (2) writing “1” to the SOFT_RST bit in the Receive Control Register, this reset bit is not a self-clearing bit, reset

can be terminated by writing the bit low. It programs all registers to their default value. When reset is initiated by (1) and

the EEPROM is presented and enabled, the controller will load the EEPROM to obtain the following configurations: 1)

Configuration Register, 2) BASE Register, or/and 3) MAC Address. The internal MAC is not a power on reset device,

thus reset is required after power up to ensure all register bits are in default state.

The internal PHY is reset when either (1) VDD is applied to the device, (2) the RST bit is set in the PHY Ml serial port

Control register, this reset bit is a self-clearing bit, and the PHY will return a “1” on reads to this bit until the reset is

completed, 3) the RESET pin is asserted high, (4) the SOFT_RST bit is set high and then cleared. When reset is initiated

by (1) or (2), an internal power-on reset pulse is generated which resets all internal circuits, forces the PHY Ml serial

port bits to their default values, and latches in new values for the MI address. After the power-on reset pulse has finished,

the reset bit in the PHY Ml serial port Control registers cleared and the device is ready for normal operation. When reset

is initiated by (3), the same procedure occurs except the device stays in the reset state as long as the RESET pin is

held high. The internal PHY is ready for normal operation 50 mS after the reset pin was de-asserted or the reset bit is

set. Software driver requires to wait for 50mS after setting the RST bit to high to access the internal PHY again.

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