PC87591L datasheet(220/437 Pages) NSC

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Access Paths

The flash memory can be read, written and erased through several access paths with different levels of protection for the

flash contents. Each of these paths can be operational in only some of the environments (i.e., IRE, OBD, DEV or PROG).

The flash access paths are:

●

Host interface

●

CR16B core

●

JTAG ﬂash access

●

Parallel interface

The host and core use core bus read write transactions to access the flash. The JTAG and Parallel Interfaces have dedicated

access paths. An arbitration scheme selects the active interface that accesses the flash at any given time. The host and core

accesses may interleave. JTAG flash access is enabled in OBD and ENV environments when the appropriate enable bits

are set (see “Flash Interface Functional Description” on page 251 for the access enabling scheme). The Parallel interface

is enabled in PROG environment only.

Table 30 summarizes the flash information accessibility, the restrictions that apply in the various environments and the pro-

tection bit settings for each of the memory areas. Details of read, write and erase access are provided in Section 4.16.4 on

page 224. The following notation is used:

- Not accessible

- Read only

- Read, Write

RWE - Read, Write and Erase

RWe

- Read, Write and a limited Erase (i.e., entire flash erase only).

Figure 76. On-Chip Flash Block Diagram

Arbitration

Protection

Timing

Access

Control

Shared BIOS

and

Security

Core Bus

JTAG I/F

Parallel I/Fs

Core

Main Block

Information Block

To Host

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