PC87591L datasheet(18/437 Pages) NSC

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Table of Contents (Continued)

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Revision 1.07

MSWC Control Status Register 1 (MSWCTL1) ................................................. 329

MSWC Control Status Register 2 (MSWCTL2) ................................................. 330

MSWC Control Status Register 3 (MSWCTL3) ................................................. 330

Host Configuration Base Address Low (HCFGBAL) .......................................... 331

Host Configuration Base Address High (HCFGBAH) ........................................ 331

MSWC Interrupt Enable Register 2 (MSIEN2) ................................................... 331

MSWC Host Event Status Register 0 (MSHES0) .............................................. 332

MSWC Host Event Interrupt Enable Register (MSHEIE0) ................................. 333

5.5.7

Usage Hints ............................................................................................................... 334

PWUREQ Output Connection ............................................................................ 334

RESET2 Events ................................................................................................. 334

6.0

Host-Controlled Modules and Host Interface

6.1

DEVICE ARCHITECTURE AND CONFIGURATION .............................................................. 335

6.1.1

Configuration Structure and Access .......................................................................... 335

The Index-Data Register Pair ............................................................................ 335

Banked Logical Device Registers Structure ...................................................... 336

Standard Logical Device Configuration Register Definitions ............................. 337

6.1.2

Standard Configuration Registers ............................................................................. 340

SuperI/O Control and Configuration Registers .................................................. 340

Logical Device Control and Configuration Registers ......................................... 340

Control ............................................................................................................... 340

Standard Configuration ...................................................................................... 341

Special Configuration ......................................................................................... 341

6.1.3

Default Configuration Setup ...................................................................................... 341

6.1.4

Address Decoding ..................................................................................................... 341

6.1.5

Interrupt Serializer ..................................................................................................... 342

6.1.6

Protection .................................................................................................................. 342

6.1.7

LPC Interface ............................................................................................................. 342

LPC Transactions Supported ............................................................................. 342

Core Interrupt ..................................................................................................... 343

CLKRUN Functionality ....................................................................................... 343

LPCPD Functionality .......................................................................................... 343

6.1.8

SuperI/O Configuration Registers .............................................................................. 343

SuperI/O ID Register (SID) ................................................................................ 344

SuperI/O Configuration 1 Register (SIOCF1) .................................................... 344

SuperI/O Configuration 5 Register (SIOCF5) .................................................... 345

SuperI/O Configuration 6 Register (SIOCF6) .................................................... 345

SuperI/O Revision ID Register (SRID) ............................................................... 346

SuperI/O Configuration 8 Register (SIOCF8) .................................................... 346

SuperI/O Configuration 9 Register (SIOCF9) .................................................... 347

SuperI/O Configuration D Register (SIOCFD) ................................................... 347

6.1.9

Mobile System Wake-Up Control (MSWC) Configuration ......................................... 348

Logical Device 4 (MSWC) Configuration ........................................................... 348

6.1.10

Keyboard and Mouse Controller (KBC) Configuration ............................................... 348

Logical Devices 5 and 6 (Mouse and Keyboard) Configuration ......................... 348

6.1.11

Shared Memory Configuration ................................................................................... 349

Logical Device 15 (0F16) (Shared Memory) Configuration ................................ 349

Memory Range Programing ............................................................................... 350

Shared Memory Configuration Register ............................................................ 351

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