PC87591L datasheet(98/437 Pages) NSC

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Embedded Controller Modules (Continued)

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4.3

INTERRUPT CONTROL UNIT (ICU)

The ICU has 31 channels. It interfaces between the different modules’ interrupt requests and external interrupt requests and

also generates the core interrupt. It generates both maskable and non-maskable interrupts. The ICU has a predetermined

scheme that allocates priority.

4.3.1

Features

Non-Maskable Interrupts (NMI)

●

Gathers all edge-triggered non-maskable interrupt sources

— External Power Fail (PFAIL) interrupt source

●

Holds the status of the current pending NMI requests

●

Generates non-maskable interrupt (NMI) to the core

Maskable Interrupts

●

31 active high-level or edge-triggered interrupt sources

●

Core vectored interrupt mode

●

Fixed priority among interrupt sources

●

Individual enable/disable for each interrupt source

●

Polling support by an interrupt status register

●

Clear registers for edge-triggered interrupts

4.3.2

Non-Maskable Interrupt (NMI)

The Interrupt Control Unit (ICU) gathers external non-maskable interrupt (NMI) sources and generates an NMI interrupt to

the core when required.

External NMI Inputs

The ICU processes the PFAIL signal to send to the CR16B NMI input.

Non-Maskable Interrupt Processing

The CR16B core performs an “Interrupt Acknowledge” bus cycle when beginning to process a non-maskable interrupt. The

address associated with this core bus cycle is within the internal core address space and may be monitored as a Core Bus

Monitoring (CBM) clock cycle. For additional details, see “Core Bus Monitoring” on page 82 and Section 4.20.6 on page 273.

After reset, NMI is disabled and must remain disabled until the software initializes the interrupt table, interrupt base and the

interrupt mode.

The PFAIL interrupt is enabled by setting ENLCK bit and remains enabled until a reset occurs. This allows the external NMI

feature to be enabled only after the Interrupt Base Register (IMASK) and the Interrupt Stack Pointer (ISP), in the core, have

been set up.

Alternatively, the external PFAIL interrupt can be enabled by setting EN bit, which remains enabled until an interrupt event

or a reset occurs. The NMISTAT register holds the status of the current pending NMI request. When the bit in NMISTAT is

set to 1, an NMI request to the core is issued. NMISTAT is cleared each time its contents are read. NMI handlers must read

the NMISTAT register to allow new NMI events to occur.

Note that PFAIL status bit in NMISTAT register may be set as a result of transient enable conditions on PFAIL. To avoid an

interrupt to the core, after configuring the PFAIL input for operation, read the NMISTAT register and then enable PFAIL by

writing 1 to EN bit in PFAIL register.

PFAIL Input

The PFAIL signal is an asynchronous input with Schmitt trigger characteristics and an internal synchronization circuit; there-

fore, no external synchronizing circuit is needed. The PFAIL signal generates an interrupt on its falling edge.

4.3.3

Maskable Interrupts

The ICU receives level or edge-triggered interrupt request signals from 31 sources and generates a vectored interrupt to the

CR16B core when required. Priority among the interrupt sources (named INT1 to INT31) is fixed. Each interrupt source can

be individually enabled or disabled under software control through:

●

ICU interrupt enable registers

●

Interrupt enable bits in the peripherals that request the interrupts.

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