PC87591L datasheet(26/437 Pages) NSC

26 / 437 page

1.0 Introduction (Continued)

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Revision 1.07

Figure 2. PC87591x Functional Block Diagram

1.3.1

Processing Unit

The CompactRISC CR16B core (referred to in this datasheet as the “core”) is an advanced, general-purpose 16-bit micro-

processor core with a RISC architecture. The core is responsible for arithmetic and logic operations, as well as program

control.

For more details about the core structure and instruction set, see CR16B Programmer’s Reference Manual, Revision 2.2,

September 1999 (Literature Number: 633150-001)

1.3.2

Bus Interface Unit and Memory Controller (BIU)

The BIU enables access to off-chip memory and I/O devices. It is organized in zones, as follows:

●

Zone 0 - Expansion Memory (ﬂash and/or SRAM). This memory may be used for the core code, data and/or the host

BIOS program.

●

Zone 1 - This zone is available for off-chip in DEV environment only and is used for emulating the operation of the

off-chip base memory, using an off-chip SRAM. In IRE and OBD environments, the conﬁguration of this zone should

be the same as in DEV environment to enable cycle-by-cycle compatibility.

The Base memory is partitioned into two zones, fast and slow. The access time to the fast zone is defined by the con-

figuration registers of Zone 1 in the BIU. The access time to the slow zone is defined by the configuration registers of

Zone 2 in the BIU. Only one chip select signal is used—the AND of the two BIU select outputs.

●

I/O Zone - This zone can be used for I/O expansion. In DEV environment, it can be used to recreate GPIO signals,

whose pins are used for the development system interface.

Configuration registers that control the bus transactions are associated with each zone and are part of the BIU module, See

Section 4.1 on page 69 for details. For details about the link between DEV environment and the BIU, see Section 1.4.3 on

page 30.

1.3.3

On-Chip Memory

RAM. The 2048/4096-byte on-chip RAM is mostly used for the storage of program variables and the stack. It can also store

short programs used while the flash memory is being updated. Part of the on-chip RAM is reserved for use by the core de-

velopment tools monitor program, TMON. For information, see the CompactRISC

 PC87591x Tmonlib Version 3.1.2.3 Re-

lease Letter, March 2001,

Flash. The PC87591E and PC87591S are equipped with a large on-chip flash. This flash includes a main block and an in-

formation block. The flash main block is also referred to as on-chip Base Memory and may be used to store core code and

constant data.

Core Bus

Peripheral Bus

Bus

KBC + PM

Host I/F

RTC

Processing

Unit

RAM

External

BIU

CR16B Core

32.768 KHz

ICU

HFCG

PMC

ADC

ACB

GPIO

WDG

FLASH or ROM

MIWU

Memory + I/O

MFT16

Timer +

Adapter

PS/2

I/F

(X2)

CLK

DAC

(X2)

Memory

Debugger

I/F

Shared mem.

+ Security

LPC

I/F

Serial

IRQ

SMI

Functions

Internal Bus

CR Access

DMA

JTAG

KBSCAN +

ACM

USART

Peripherals

LPC Bus I/F

I/F Functions

PWM

Reset &

Config

MSWC

Bridge

Controlled

Host

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