PC87591L datasheet(69/437 Pages) NSC

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4.0

Embedded Controller Modules

4.1

BUS INTERFACE UNIT (BIU)

The BIU directly interfaces with a wide variety of devices, including ROM, SRAM and flash memory devices and I/O devices.

It interfaces via address, data and control buses without the need for external glue logic.

The BIU also defines the access time to the on-chip flash Main block to provide cycle-by-cycle compatibility between envi-

ronments; see Section 1.4 on page 29 and “Accessing Base Memory” on page 35. To optimize access time to the on-chip

Base Memory, the Base Memory is split into Fast and Slow Zones. These zones are associated with Zone 1 and Zone 2 of

the BIU, respectively. The SEL1 output signal of the PC87591x is the logical AND of the two SELi outputs of Zones 1 and 2.

4.1.1

Features

●

Four address zones for static devices (SRAM, ROM, ﬂash, I/O).

●

Basic bus cycle: two clock cycles.

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Conﬁgurable fast read bus cycles with 1-cycle read duration.

●

Wait states: conﬁgurable between zero and seven clock cycles.

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Hold cycles: conﬁgurable between zero and three clock cycles.

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I/O expansion support.

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Conﬁgurable burst on read.

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Burst read: one clock cycle.

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Conﬁgurable early write or late write.

●

Bus width: conﬁgurable per zone - 16-bit or 8-bit.

4.1.2

Functional Description

Interface

The BIU interfaces between:

●

Internal core bus

●

External static memory

●

Off-chip I/O (memory-mapped) devices

The BIU performs the following functions:

●

Distinguishes between four static memory zones

●

Selects the relevant conﬁgured parameters of the accessed zone (e.g., the number of wait states)

●

Issues the appropriate bus cycle to access the zone

Each memory zone has a different address range and a set of parameters that define access to this zone. The set of pa-

rameters is software configurable.

Static Memory and I/O Support

The BIU accesses static memory devices (ROM, SRAM, flash and I/O devices) using static read and write bus cycles. The

BIU can be configured to extend the bus cycles with wait cycles.

The BIU supports burst read bus cycles if the accessed zone is configured as burstable. (A burst-read bus cycle is an ex-

tension of the basic-read bus cycle in which additional data is accessed. A burst access usually requires only one clock cycle

per additional data item. It may be extended by up to two clock cycles per additional data item.)

To support both I/O and static memory devices that require long hold times at the end of the access, the BIU can be config-

ured to add up to three Thold clock cycles at the end of the bus cycle. In addition, the BIU can be configured to insert a Tidle

clock cycle between two consecutive accesses to different zones.

Byte Access

The internal core bus is 16-bits wide and supports byte and word transactions.

The BIU issues the appropriate bus cycle to access the right bytes, according to the core bus transaction and the memory de-

vice bus width. Table 13 and Table 14 summarize the details:

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