PC87591L datasheet(43/437 Pages) NSC

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2.0 Signal/Pin Description and Configuration (Continued)

Revision 1.07

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2.2.4

Core Bus Interface Unit (BIU)

Signal

128-Pin

LQFP

176-Pin

LQFP

I/O

Buffer

Type

Power

Well

Description

A3-0

95-92

127-124

O1/2

VCC Address Bus, bits 0-19. Core external address

bus. Affected or used by any transaction on the

internal core-bus, including DMA transactions

and accesses to the internal memory.

A19-8

N/A

103-104

112-113

120-121

129-130

134-135

142-143

A7-4

99-96

133-131,

128

OO2/12

VCC

D7-4,

D3-0

109-

102

147-144

141-138

I/O

INT/O1/2

VCC Data bus, bits 0-15. Core external data bus.

Used for core access to external memory or I/O

devices. When accessing an 8-bit external

memory or I/O device, only D0-7 should be

used.

D15-14,

D13-12,

D11-10,

D9-8

N/A

149-148

156-155

4-3

28-27

110

150

O1/2

VCC Read Control. Core external read strobe. Can

be used as output enable for external memory

of I/O devices.

SEL0

N/A

173

O1/2

VCC Zone Select 0. Chip-select signal for external

memory devices mapped to zone 0.

SEL1

N/A

174

O1/2

VCC Zone Select 1. Chip-select signal for external

memory devices mapped to zones 1 and 2

(Base Memory). Available in DEV environment

for off-chip emulation of the on-chip ﬂash or

ROM. In IRE and OBD environments, zones 1

and 2 are mapped to the on-chip ﬂash or ROM

and SEL1 output is inactive.

SELIO

112

152

O1/2

VCC I/O Zone Select. Chip-select signal for external

I/O devices mapped to this zone. Can be used

for mapping off-chip I/O expansion devices to

the core address space.

WR1

N/A

O1/2

VCC Write Control 1 and 0. Indicates writes to bytes

1 and 0, respectively, of the BIU data bus.

WR0

111

151

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