PC87591L datasheet(30/437 Pages) NSC

30 / 437 page

1.0 Introduction (Continued)

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Revision 1.07

See Figure 1 on page 24 for a system example in IRE environment. In this environment, the ENV0, ENV1 and TRIS strap

pins do not need any external pull-up resistors.

1.4.2

OBD Environment

OBD environment is used for debugging the PC87591x firmware while it is mounted on its final production board. All pins

have their IRE functionality, and the interface to a debugger running on the host is enabled using the JTAG based debugger

interface. In OBD Environment, code is executed from the on-chip flash memory. Breakpoints on data and code access may

be applied using the core hardware breakpoint mechanism. The monitor stored in the on-chip flash is used as part of the

debugging environment. Erasing and reprograming the flash is enabled through the JTAG-based debugger interface.

OBD environment is binary and cycle-by-cycle compatible with IRE environment.

See Figure 3 on page 31 for a system example in OBD environment. In this environment, the ENV0 and TRIS strap pins are

left unconnected, and ENV1 requires an external pull-up resistor. If the flash Contents Protect bit in the protection word is

cleared (0), the PC87591x remains reset until the bit is set; see Section 4.16.6 on page 226.

1.4.3

DEV Environment

DEV environment is used in Application Development Boards (ADBs) or In System Emulators (ISEs). It may only be used

when the chip is packed in its 176-pin package. In this mode, the on-chip flash is replaced with off-chip SRAM memory to

allow flexible and fast development of application code. Some pins are allocated for development system use, and the GPIO

functions associated with the pins are replicated using off-chip logic as part of the ADB system. DEV environment is binary

and cycle-by-cycle compatible with OBD and IRE environments.

In this environment, the pins of ports PH, PI, PJ, PK, PL and PM are allocated for the interface to the off-chip Base Memory,

core status signals, reset output and a breakpoint input. The system may regain these ports using the I/O Expansion protocol

and off-chip logic, while maintaining cycle-by-cycle and binary compatibility with IRE and OBD environments. Using the

same software, this environment is binary and cycle-by-cycle compatible with IRE and OBD environments. All features of

IRE environment can be implemented either directly or by using additional external logic.

See Figure 4 on page 32 for a system example in DEV environment. In this environment, the ENV0 strap pin needs an ex-

ternal pull-up resistor and the ENV1 and TRIS pins are left unconnected. If the flash Contents Protect bit in the protection

word is cleared (0), the PC87591x remains reset until the bit is set; see Section 4.16.6 on page 226.

1.4.4

PROG Environment

PROG environment is used to program the on-chip flash. It can be used to program the on-chip flash with an external flash

programer. In PROG environment, the PC87591x remains reset indefinitely, I/O pins are allocated for the on-chip flash in-

terface ports and the on-chip flash interface is accessible directly through the I/O pins.

In this environment, both ENV0 and ENV1 strap pins need an external pull-up resistor. The TRIS pin can be either left un-

connected or connected to a pull-down resistor.

1.5

MEMORY MAP

The PC87591x has two address domains: core and host. The host address space is composed of the host I/O address space

and the host memory space. Section 1.5.1 discusses the mapping of memories and peripherals into the core address space.

Figure 5 illustrates the memory map and the shared access schemes that are possible. Section 1.5.2 discusses the mapping

of the host address space and ways of accessing it. The PC87591x enables several memories in the core address space

to have restricted access to the host. These memories are referred to as “shared memory” or “shared BIOS”. In addition, the

core can access the Host Controlled Functions. Section 1.5.2 and Section 1.5.3 discuss these instances of cross-domain

access, respectively.

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