PC87591L datasheet(92/437 Pages) NSC

92 / 437 page

Embedded Controller Modules (Continued)

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Auto-Initialize Operation

This mode allows the DMAC to continuously fill the same memory area without software intervention.

Initialization

1. Write the two block addresses and byte count into the ADCAn, ADCBn and BLTCn counters, respectively (the BLTCn

counter should be written last); also write them to the ADRAn, ADRBn and BLTRn registers, respectively (the BLTRn

counter should be written last).

2. Program OT bit in DMACNTLn register for Auto-Initialize mode.

3. Set CHEN bit in DMACNTLn register to 1; the channel activates and responds to DMAC transfer requests.

Continuation

When the BLTCn counter reaches 0:

●

The contents of the ADRAn, ADRBn and BLTRn registers are copied to the ADCAn, ADCBn and BLTCn counters,

respectively. The BLTCn counter should be written last.

●

The DMAC channel checks the value of TC bit.

If TC bit is 1:

●

OVR bit in DMASTATn register is set to 1.

●

A level interrupt is generated (if enabled by EOVR bit in DMACNTLn register).

●

The operation is repeated.

If TC bit is 0:

●

TC bit in DMASTATn register is set to 1.

●

A level interrupt is generated (if enabled by ETC bit in DMACNTLn register).

●

The operation is repeated.

4.2.7

Software DMA Request

In addition to the DMRQn signals, a DMA transfer request can also be initiated by software. The software DMA transfer re-

quest is used for memory-to-memory block copying (in indirect transfers).

When SWRQ bit in DMACNTLn register is 1, the corresponding DMA channel receives a DMA transfer request. When

SWRQ bit is 0, the software DMA transfer request of the corresponding channel is inactive.

For each channel, use the software DMA transfer request, only when the corresponding DMRQn signal is inactive.

4.2.8

DMAC Registers

For a summary of the abbreviations used for Register Type, see “Register Abbreviations and Access” on page 34.

DMAC Register Map

Note:

Unless stated otherwise, bits 21 to 31 are reserved in each of the following registers. Double-word (32-bit) registers may be

accessed word-by-word (word aligned).

Mnemonic

Type

ADCAn

Device A Address Counter Register

R/W

ADRAn

Device A Address Register

R/W

ADCBn

Device B Address Counter Register

R/W

ADRBn

Device B Address Register

R/W

BLTCn

Block Length Counter Register

R/W

BLTRn

Block Length Register

R/W

DMACNTLn

DMA Control Register

R/W

DMASTATn

Status Register

R/W

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