PC87591L datasheet(58/437 Pages) NSC

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2.0 Signal/Pin Description and Configuration (Continued)

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Revision 1.07

2.4.2

System Configuration Registers

For a summary of the abbreviations used for Register Type, see Section 2 on page 34.

Module Conﬁguration Register (MCFG)

The MCFG register is a read/write, byte-wide register. It is used for global system configuration and setup.

Write operations to the MCFG register should write zeros to all reserved bits. On reset, non-reserved bits of MCFG are

cleared to 0. MCFG can be written in Active mode only. Its contents is preserved in Idle mode.

In IRE and OBD environments, all MCFG fields should be used to designate associated pins as GPIO ports or their alternate

functions. In DEV environment, the pins are always allocated for development system use. The I/O ports functionality can

be implemented using off-chip logic.

To guarantee binary and cycle-by-cycle compatibility among the different environments, define the MCFG fields as required

for IRE and OBD even when in DEV environment, and use the I/O Expansion protocol to build an off-chip implementation

of the I/O ports when they are used by the application.

ADBs or ISE systems use the MCFG Shadow (MCFGSH, write only) register to select the functionality of the signal that

reaches the user’s application.

All write operations to the MCFG must be immediately followed by a write to the MCFG Shadow (MCFGSH) register. This

MCFG is loaded with either 0016 or 8016 on reset. See the description of GTMON for behavior of bit 7 during reset.

Software should load MCFGSH with the MCFG register’s value after reset.

The format of MCFG (and MCFGSH) is as follows:

MCFG Location: 00 FF1016

MCFGSH Location: 00 FBFE16

Type: R/W

Mnemonic

Type

MCFG

Module Conﬁguration Register

R/W

EICFG

External Interrupts Conﬁguration Register

R/W

IOEE1 and

IOEE2

Input to Output Echo Enable Register 1 and 2

R/W

Bit

76543210

Name

GTMON

Reserved

CLKOM

EXMEM16

ENEMEM

ENEIO

Reset

See text

0000000

Bit

Description

ENEIO (Enable Expansion I/O). Enables the use of the I/O Expansion protocol for expanding the amount of

GPIO pins available to the application. In IRE and OBD environments, when ENEIO is cleared, the associated

pins are used as GPIO signals. When set, enables the use of BIU I/O Zone (SELIO) for the interface with off-

chip logic. Use the BIU I/O Zone conﬁguration to select the access parameters to the I/O Expansion logic and

its bus width.

ENEMEM (Enable Expansion Memory). Enables the use of the Expansion memory for expanding the amount

of memory available to the application to more than what is provided on chip. When cleared, the associated pins

are used as GPIO signals. When set, enables the use of BIU Zone 0 (SEL0) and the associated address and

data lines for the interface with ﬂash or SRAM devices. Use BIU Zone 0 conﬁguration to select the access

parameters to the Expansion memory and its width.

Set this bit in the 176-pin package only.

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