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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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PC87591L bảng dữ liệu(PDF) 100 Page - National Semiconductor (TI) |
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PC87591L bảng dữ liệu(HTML) 100 Page - National Semiconductor (TI) |
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100 / 437 page  Embedded Controller Modules (Continued) www.national.com 100 Revision 1.07 INT8 Internal Level-High ADC interrupt (ADCI) INT9 Internal Level-High ACCESS.bus 1 interrupt INT10 Internal Level-High ACCESS.bus 2 interrupt INT11 MIWU Level-High Internal Keyboard Scan Interrupt (KBSINT from MIWU) or ACM Interrupt INT12 Internal/MIWU Level-High MSWC interrupt through the MIWU INT13 Internal/MIWU Edge Rising TWM system tick (T0OUT), through the MIWU2 INT14 External/MIWU Level-High SWIN input1, through the MIWU INT15 Reserved INT16 Internal Level-High USART Interrupt (TX Int OR RX int) INT17 External/MIWU Level-High External Interrupt EXWINT24 through the MIWU1 INT18 Internal Edge Falling PS/2 shift mechanism (PSINT3) INT19 Internal Edge Falling PS/2 shift mechanism (PSINT2) INT20 Internal Level High / Edge Falling3 PS/2 shift mechanism (PSINT1) INT21 External/MIWU Level-High External Interrupt EXWINT22 through the MIWU1 INT22 Internal Level-High MFT16 2 Interrupt (INT1 ORed with INT2) INT23 Internal Level-High Flash I/F interrupt or Shared Memory Interrupt INT24 Internal Level-High Host I/F Keyboard/Mouse channel Input Buffer Full INT25 Internal Level-High Host I/F Power Management channel 1 or channel 2 Input Buffer Full INT26 Reserved INT27 Internal Level-High DMA Channel 0 INT28 Internal Level-High DMA Channel 1 INT29 Reserved INT30 Reserved INT31 External/MIWU Level-High External Interrupt EXWINT21 through the MIWU1 Highest 1. To enable the external interrupt, set the pin to its alternate function. When used as I/O port signals the External interrupt input is forced to 0 2. When in Active mode, it is advised to disable the T0OUT channel of the MIWU, this saves the need to clear the pending bit in the MIWU on each interrupt. 3. Falling Edge is enabled for this input when the PS/2 channel ‘Disabled Shift Mechanism Interrupts’ are enabled (DSMIE in PSIEN register = 1) Table 16. ICU Interrupt Assignments (Continued) INT Number Source Type Details Priority |
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