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PC87591L bảng dữ liệu(PDF) 217 Page - National Semiconductor (TI) |
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PC87591L bảng dữ liệu(HTML) 217 Page - National Semiconductor (TI) |
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217 / 437 page ![]() Embedded Controller Modules (Continued) Revision 1.07 217 www.national.com Voltage Level Data Buffer - Input 0 through 7 (VOLDAT0-7) This register holds the voltage level measurement result for inputs 0 through 7. Location: 00 FD5016 - Input 0 00 FD5216 - Input 1 00 FD5416 - Input 2 00 FD5616 - Input 3 00 FD5816 - Input 4 00 FD5A16 - Input 5 00 FD5C16 - Input 6 00 FD5E16 - Input 7 Type: RO 4.14.6 Usage Hints Voltage Level Burst The total duration of the Voltage Level Burst measurement is a function of the system clock frequency (see Section 4.18 on page 239) and the data sampling delay, selected by SMPDLY field in ACMTIM register. The values in Table 28 should only be used to evaluate the maximum duration of the measurement. Actual duration may be shorter, depending on the input level value. The software should use either EOMEV flag polling or the ACM interrupt, as described in Section 4.14.4 on page 210. Table 28. Voltage Level Burst Duration Bit 76543210 Name Reserved VOLTLVL Bit Description 5-0 VOLTLVL (Voltage Level Data). Voltage level of the respective input i (KBSINi for i 0 through 7), while operating in Voltage Level Burst mode (ACMMOD = 012 in ACMCNF register). The readout is an unsigned value with 1 LSB = VCC/64; the input voltage is calculated as: VIN = VOLTVL * (VCC/64). 7-6 Reserved. System Clock Frequency (MHz) SMPDLY Setting Maximum Burst Duration ( µs) 4 000 176 10 010 140 20 101 118 |
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