 |
công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
|
công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
TMP320C2811PBKA bảng dữ liệu(PDF) 135 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
TMP320C2811PBKA bảng dữ liệu(HTML) 135 Page - Texas Instruments |
|
|
135 / 147 page  Electrical Specifications 135 June 2004 SPRS257 6.30 Multichannel Buffered Serial Port (McBSP) Timing 6.30.1 McBSP Transmit and Receive Timing Table 6−43. McBSP Timing Requirements†‡ NO. MIN MAX UNIT McBSP module clock (CLKG CLKX CLKR) range 1 kHz McBSP module clock (CLKG, CLKX, CLKR) range 20§ MHz McBSP module cycle time (CLKG CLKX CLKR) range 50 ns McBSP module cycle time (CLKG, CLKX, CLKR) range 1 ms M11 tc(CKRX) Cycle time, CLKR/X CLKR/X ext 2P ns M12 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext P-7 ns M13 tr(CKRX) Rise time, CLKR/X CLKR/X ext 7 ns M14 tf(CKRX) Fall time, CLKR/X CLKR/X ext 7 ns M15 t Setup time external FSR high before CLKR low CLKR int 18 ns M15 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low CLKR ext 2 ns M16 t Hold time external FSR high after CLKR low CLKR int 0 ns M16 th(CKRL-FRH) Hold time, external FSR high after CLKR low CLKR ext 6 ns M17 t Setup time DR valid before CLKR low CLKR int 18 ns M17 tsu(DRV-CKRL) Setup time, DR valid before CLKR low CLKR ext 2 ns M18 t Hold time DR valid after CLKR low CLKR int 0 ns M18 th(CKRL-DRV) Hold time, DR valid after CLKR low CLKR ext 6 ns M19 t Setup time external FSX high before CLKX low CLKX int 18 ns M19 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low CLKX ext 2 ns M20 t Hold time external FSX high after CLKX low CLKX int 0 ns M20 th(CKXL-FXH) Hold time, external FSX high after CLKX low CLKX ext 6 ns † Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ‡ 2P = 1/CLKG in ns. CLKG is the output of sample rate generator mux. CLKG = CLKSRG (1 ) CLKGDV) . CLKSRG can be LSPCLK, CLKX, CLKR as source. CLKSRG ≤ (SYSCLKOUT/2). McBSP performance is limited by I/O buffer switching speed. § Internal clock prescalers must be adjusted such that the McBSP clock (CLKG, CLKX, CLKR) speeds are not greater than the I/O buffer speed limit (20 MHz). |
|
Link URL |
| Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Liên kết đến bảng dữ liệu | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Vietnamese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
