TMP320C2811PBKA datasheet(133/147 Pages) TI

133 / 147 page

Electrical Specifications

133

June 2004

SPRS257

6.29.7 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)

In simultaneous mode, the ADC can continuously convert input signals on any one pair of channels (A0/B0

to A7/B7). The ADC can start conversions on event triggers from the Event Managers (EVA/EVB), software

trigger, or from an external ADCSOC signal. If the SMODE bit is 1, the ADC will do conversions on two selected

channels on every Sample/Hold pulse. The conversion time and latency of the Result register update are

explained below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result register update.

The selected channels will be sampled simultaneously at the falling edge of the Sample/Hold pulse. The

Sample/Hold pulse width can be programmed to be 1 ADC clock wide (minimum) or 16 ADC clocks wide

(maximum).

NOTE: In Simultaneous mode, the ADCIN channel pair select has to be A0/B0, A1/B1, ...,

A7/B7, and not in other combinations (such as A1/B3, etc.).

Analog Input on

Channel Ax

Analog Input on

Channel Bv

ADC Clock

Sample and Hold

SH Pulse

tSH

tdschA0_n

tdschB0_n

tdschB0_n+1

Sample n

Sample n+1

Sample n+2

tdschA0_n+1

td(SH)

ADC Event Trigger

from EV or Other

Sources

SMODE Bit

Figure 6−37. Simultaneous Sampling Mode Timing

Table 6−42. Simultaneous Sampling Mode Timing

SAMPLE n

SAMPLE n + 1

AT 25-MHz ADC

CLOCK,

tc(ADCCLK) = 40 ns

REMARKS

td(SH)

Delay time from event

trigger to sampling

2.5tc(ADCCLK)

tSH

Sample/Hold width/

Acquisition Width

(1 + Acqps) *

tc(ADCCLK)

40 ns with Acqps = 0

Acqps value = 0-15

ADCTRL1[8:11]

td(schA0_n)

Delay time for first result

to appear in Result

4tc(ADCCLK)

160 ns

td(schB0_n)

Delay time for first result

to appear in Result

5tc(ADCCLK)

200 ns

td(schA0_n+1)

Delay time for

successive results to

appear in Result register

(3 + Acqps) *

tc(ADCCLK)

120 ns

td(schB0_n+1)

Delay time for

successive results to

appear in Result register

(3 + Acqps) *

tc(ADCCLK)

120 ns

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