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TMP320C2811PBKA bảng dữ liệu(PDF) 44 Page - Texas Instruments

tên linh kiện TMP320C2811PBKA
Giải thích chi tiết về linh kiện  TMS320R2811, TMS320R2812 Digital Signal Processors
PDF  147 Pages
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TMP320C2811PBKA bảng dữ liệu(HTML) 44 Page - Texas Instruments

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Functional Overview
44
June 2004
SPRS257
3.7
System Control
This section describes R281x oscillator, PLL and clocking mechanisms, the watchdog function and the low
power modes. Figure 3−7 shows the various clock and reset domains in R281x devices that will be discussed.
HSPCLK
PLL
X1/XCLKIN
X2
Power
Modes
Control
Watchdog
Block
C28x
CPU
Low-Speed Peripherals
SCI-A/B, SPI, McBSP
Peripheral
Registers
High-Speed Peripherals
EV-A/B
High-Speed Prescaler
Low-Speed Prescaler
Clock Enables
GPIO
MUX
System
Control
Registers
Peripheral
Registers
XF_XPLLDIS
ADC
Registers
12-Bit ADC
16 ADC Inputs
HSPCLK
LSPCLK
I/O
I/O
Peripheral Reset
SYSCLKOUT
XRS
Reset
GPIOs
eCAN
Peripheral
Registers
I/O
OSC
CLKIN
NOTE A: CLKIN is the clock input to the CPU. SYSCLKOUT is the output clock of the CPU. They are of the same frequency.
Figure 3−7. Clock and Reset Domains
The PLL, clocking, watchdog and low-power modes are controlled by the registers listed in Table 3−11.



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