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TMP320C2811PBKA bảng dữ liệu(PDF) 99 Page - Texas Instruments

tên linh kiện TMP320C2811PBKA
Giải thích chi tiết về linh kiện  TMS320R2811, TMS320R2812 Digital Signal Processors
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TMP320C2811PBKA bảng dữ liệu(HTML) 99 Page - Texas Instruments

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Electrical Specifications
99
June 2004
SPRS257
† XCLKOUT = SYSCLKOUT
NOTES: A. IDLE instruction is executed to put the device into HALT mode.
B. The PLL block responds to the HALT signal. SYSCLKOUT is held for another 32 cycles before the oscillator is turned off and the
CLKIN to the core is stopped. This 32-cycle delay enables the CPU pipe and any other pending operations to flush properly.
C. Clocks to the device are turned off and the internal oscillator and PLL are shut down. The device is now in HALT mode and
consumes absolute minimum power.
D. When XNMI is driven active (negative edge triggered shown , as an example), the oscillator is turned on; but the PLL is not
activated.
E. When XNMI is deactivated, it initiates the PLL lock sequence, which takes 131,072 X1/XCLKIN cycles.
F. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after a latency. The HALT mode is now
exited.
G. Normal operation resumes.
td(IDLE−XCOH)
32 SYSCLKOUT Cycles
X1/XCLKIN
XCLKOUT†
HALT
HALT
Wake−up Latency
Flushing Pipeline
td(INT)
A
B
C
D
Device
Status
E
G
F
PLL Lock−up Time
XNMI
Normal
Execution
tw(WAKE−XNMI)
tp
Oscillator Start-up Time
Figure 6−12. HALT Wakeup Using XNMI



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