TMP320C2811PBKA datasheet(55/147 Pages) TI

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Peripherals

June 2004

SPRS257

McBSP Receive

Interrupt Select Logic

Expand Logic

DRR1 Receive Buffer

RX FIFO

Interrupt

DRR2 Receive Buffer

RX FIFO Registers

RBR1 Register

RBR2 Register

McBSP Registers

and Control Logic

CLKX

FSX

CLKR

FSR

Compand Logic

DXR2 Transmit Buffer

RSR1

XSR2

XSR1

Peripheral Read Bus

RSR2

DXR1 Transmit Buffer

LSPCLK

MRINT

To CPU

McBSP

RX Interrupt Logic

RX FIFO _15

—

RX FIFO _1

RX FIFO _0

RX FIFO _15

—

RX FIFO _1

RX FIFO _0

McBSP Transmit

Interrupt Select Logic

TX FIFO

Interrupt

TX FIFO Registers

MXINT

To CPU

TX Interrupt Logic

TX FIFO _15

—

TX FIFO _1

TX FIFO _0

TX FIFO _15

—

TX FIFO _1

TX FIFO _0

Peripheral Write Bus

Figure 4−3. Event Manager A Functional Block Diagram (See Note A)

4.2.1

General-Purpose (GP) Timers

There are two GP timers. The GP timer x (x = 1 or 2 for EVA; x = 3 or 4 for EVB) includes:

•

A 16-bit timer, up-/down-counter, TxCNT, for reads or writes

•

A 16-bit timer-compare register, TxCMPR (double-buffered with shadow register), for reads or writes

•

A 16-bit timer-period register, TxPR (double-buffered with shadow register), for reads or writes

•

A 16-bit timer-control register,TxCON, for reads or writes

•

Selectable internal or external input clocks

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