TMP320C2811PBKA datasheet(45/147 Pages) TI

45 / 147 page

Functional Overview

June 2004

SPRS257

Table 3−11. PLL, Clocking, Watchdog, and Low-Power Mode Registers†

NAME

ADDRESS

SIZE (x16)

DESCRIPTION

reserved

0x00 7010

0x00 7017

reserved

0x00 7018

reserved

0x00 7019

HISPCP

0x00 701A

High-Speed Peripheral Clock Prescaler Register for HSPCLK clock

LOSPCP

0x00 701B

Low-Speed Peripheral Clock Prescaler Register for LSPCLK clock

PCLKCR

0x00 701C

Peripheral Clock Control Register

reserved

0x00 701D

LPMCR0

0x00 701E

Low Power Mode Control Register 0

LPMCR1

0x00 701F

Low Power Mode Control Register 1

reserved

0x00 7020

PLLCR

0x00 7021

PLL Control Register‡

SCSR

0x00 7022

System Control & Status Register

WDCNTR

0x00 7023

Watchdog Counter Register

reserved

0x00 7024

WDKEY

0x00 7025

Watchdog Reset Key Register

reserved

0x00 7026

0x00 7028

WDCR

0x00 7029

Watchdog Control Register

reserved

0x00 702A

0x00 702F

† All of the above registers can only be accessed, by executing the EALLOW instruction.

‡ The PLL control register (PLLCR) is reset to a known state by the XRS signal only. Emulation reset (through Code Composer Studio) will not

reset PLLCR.

3.7.1

OSC and PLL Block

Figure 3−8 shows the OSC and PLL block on R281x.

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