TMP320C2811PBKA datasheet(98/147 Pages) TI

98 / 147 page

Electrical Specifications

June 2004

SPRS257

tw(WAKE-INT)

td(WAKE-STBY)

td(IDLE−XCOH)

32 SYSCLKOUT Cycles

Wake−up

Signal

X1/XCLKIN

XCLKOUT†

STANDBY

Normal Execution

STANDBY

Flushing Pipeline

Device

Status

NOTES: A. IDLE instruction is executed to put the device into STANDBY mode.

B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for approximately 32 cycles before being turned

off. This 32−cycle delay enables the CPU pipe and any other pending operations to flush properly.

C. The device is now in STANDBY mode.

D. The external wake−up signal is driven active (negative edge triggered shown as an example).

E. After a latency period, the STANDBY mode is exited.

F. Normal operation resumes. The device will respond to the interrupt (if enabled).

Figure 6−11. STANDBY Entry and Exit Timing

Table 6−11. HALT Mode Switching Characteristics

PARAMETER

MIN

TYP

MAX

UNIT

td(IDLE-XCOH)

Delay time, IDLE instruction executed to XCLKOUT high

32 * tc(SCO)

45 * tc(SCO)

Cycles

tw(WAKE-XNMI)

Pulse duration, XNMI wakeup signal

2 * tc(CI)

Cycles

tw(WAKE-XRS)

Pulse duration, XRS wakeup signal

8 * tc(CI)

Cycles

PLL lock-up time

131072 * tc(CI) Cycles

Delay time, PLL lock to program execution resume

td(wake)

− Wake-up from SARAM

35*tc(SCO)

Cycles

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