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TMP320C2811PBKA bảng dữ liệu(PDF) 26 Page - Texas Instruments

tên linh kiện TMP320C2811PBKA
Giải thích chi tiết về linh kiện  TMS320R2811, TMS320R2812 Digital Signal Processors
PDF  147 Pages
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TMP320C2811PBKA bảng dữ liệu(HTML) 26 Page - Texas Instruments

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Introduction
26
June 2004
SPRS257
Table 2−2. Signal Descriptions† (Continued)
PIN NO.
GPIO
PERIPHERAL SIGNAL
179-PIN
GHH
AND
ZHH
176-PIN
PGF
128-PIN
PBK
I/O/Z‡
PU/PD§
DESCRIPTION
GPIOF OR XF CPU OUTPUT SIGNAL
GPIOF14
XF_XPLLDIS (O)
A11
140
101
I/O/Z
PU
This pin has three functions:
1. XF − General-purpose output pin.
2. XPLLDIS − This pin will be sampled
during reset to check if the PLL needs
to be disabled. The PLL will be
disabled if this pin is sensed low. HALT
and STANDBY modes cannot be used
when the PLL is disabled.
3. GPIO − GPIO function
GPIOG OR SCI-B SIGNALS
GPIOG4
SCITXDB (O)
P14
90
66
I/O/Z
−
GPIO or SCI asynchronous serial port
transmit data
GPIOG5
SCIRXDB (I)
M13
91
67
I/O/Z
−
GPIO or SCI asynchronous serial port
receive data
† Typical drive strength of the output buffer for all pins [except TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins] is 4 mA typical.
‡ I = Input, O = Output, Z = High impedance
§ PU = pin has internal pullup; PD = pin has internal pulldown
NOTE:
Other than the power supply pins, no pin should be driven before the 3.3-V rail has reached
recommended operating conditions. However, it is acceptable for an I/O pin to ramp along with
the 3.3-V supply.



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