TMP320C2811PBKA datasheet(41/147 Pages) TI

41 / 147 page

Functional Overview

June 2004

SPRS257

Figure 3−6 shows how the interrupts are multiplexed using the PIE block. Eight PIE block interrupts are

grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8 interrupts per group equals 96

possible interrupts. On R281x, 45 of these are used by peripherals as shown in Table 3−8.

INT12

MUX

INT11

INT2

INT1

CPU

(Enable)

(Flag)

INTx

INTx.8

PIEIERx(8:1)

PIEIFRx(8:1)

MUX

INTx.7

INTx.6

INTx.5

INTx.4

INTx.3

INTx.2

INTx.1

From

Peripherals or

External

Interrupts

(Enable)

(Flag)

IER(12:1)

IFR(12:1)

Global

Enable

INTM

PIEACKx

(Enable/Flag)

Figure 3−6. Multiplexing of Interrupts Using the PIE Block

Table 3−8. PIE Peripheral Interrupts†

CPU

PIE INTERRUPTS

CPU

INTERRUPTS

INTx.8

INTx.7

INTx.6

INTx.5

INTx.4

INTx.3

INTx.2

INTx.1

INT1

WAKEINT

(LPM/WD)

TINT0

(TIMER 0)

ADCINT

(ADC)

XINT2

XINT1

reserved

PDPINTB

(EV-B)

PDPINTA

(EV-A)

INT2

reserved

T1OFINT

(EV-A)

T1UFINT

(EV-A)

T1CINT

(EV-A)

T1PINT

(EV-A)

CMP3INT

(EV-A)

CMP2INT

(EV-A)

CMP1INT

(EV-A)

INT3

reserved

CAPINT3

(EV-A)

CAPINT2

(EV-A)

CAPINT1

(EV-A)

T2OFINT

(EV-A)

T2UFINT

(EV-A)

T2CINT

(EV-A)

T2PINT

(EV-A)

INT4

reserved

T3OFINT

(EV-B)

T3UFINT

(EV-B)

T3CINT

(EV-B)

T3PINT

(EV-B)

CMP6INT

(EV-B)

CMP5INT

(EV-B)

CMP4INT

(EV-B)

INT5

reserved

CAPINT6

(EV-B)

CAPINT5

(EV-B)

CAPINT4

(EV-B)

T4OFINT

(EV-B)

T4UFINT

(EV-B)

T4CINT

(EV-B)

T4PINT

(EV-B)

INT6

reserved

MXINT

(McBSP)

MRINT

(McBSP)

reserved

SPITXINTA

(SPI)

SPIRXINTA

(SPI)

INT7

reserved

INT8

reserved

INT9

reserved

ECAN1INT

(CAN)

ECAN0INT

(CAN)

SCITXINTB

(SCI-B)

SCIRXINTB

(SCI-B)

SCITXINTA

(SCI-A)

SCIRXINTA

(SCI-A)

INT10

reserved

INT11

reserved

INT12

reserved

† Out of the 96 possible interrupts, 45 interrupts are currently used. the remaining interrupts are reserved for future devices. However, these

interrupts can be used as software interrupts if they are enabled at the PIEIFRx level.

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