 |
công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
|
công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
TMP320C2811PBKA bảng dữ liệu(PDF) 136 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
TMP320C2811PBKA bảng dữ liệu(HTML) 136 Page - Texas Instruments |
|
|
136 / 147 page  Electrical Specifications 136 June 2004 SPRS257 Table 6−44. McBSP Switching Characteristics†‡ NO. PARAMETER MIN MAX UNIT M1 tc(CKRX) Cycle time, CLKR/X CLKR/X int 2P ns M2 tw(CKRXH) Pulse duration, CLKR/X high CLKR/X int D-5§ D+5§ ns M3 tw(CKRXL) Pulse duration, CLKR/X low CLKR/X int C-5§ C+5§ ns M4 t Delay time CLKR high to internal FSR valid CLKR int 0 4 ns M4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR ext 3 27 ns M5 t Delay time CLKX high to internal FSX valid CLKX int 0 4 ns M5 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid CLKX ext 3 27 ns M6 t Disable time, CLKX high to DX high impedance CLKX int 8 ns M6 tdis(CKXH-DXHZ) Disable time, CLKX high to DX high impedance following last data bit CLKX ext 14 ns Delay time, CLKX high to DX valid. CLKX int 9 Delay time, CLKX high to DX valid. This applies to all bits except the first bit transmitted. CLKX ext 28 DXENA 0 CLKX int 8 M7 td(CKXH-DXV) Delay time, CLKX high to DX valid DXENA = 0 CLKX ext 14 ns Only applies to first bit transmitted when in Data DXENA 1 CLKX int P + 8 Only applies to first bit transmitted when in Data Delay 1 or 2 (XDATDLY=01b or 10b) modes DXENA = 1 CLKX ext P + 14 DXENA 0 CLKX int 0 M8 t Enable time, CLKX high to DX driven DXENA = 0 CLKX ext 6 ns M8 ten(CKXH-DX) Only applies to first bit transmitted when in Data DXENA 1 CLKX int P ns Only applies to first bit transmitted when in Data Delay 1 or 2 (XDATDLY=01b or 10b) modes DXENA = 1 CLKX ext P + 6 DXENA 0 FSX int 8 M9 t Delay time, FSX high to DX valid DXENA = 0 FSX ext 14 ns M9 td(FXH-DXV) Only applies to first bit transmitted when in Data DXENA 1 FSX int P + 8 ns Only applies to first bit transmitted when in Data Delay 0 (XDATDLY=00b) mode. DXENA = 1 FSX ext P + 14 DXENA 0 FSX int 0 M10 t Enable time, FSX high to DX driven DXENA = 0 FSX ext 6 ns M10 ten(FXH-DX) Only applies to first bit transmitted when in Data DXENA 1 FSX int P ns Only applies to first bit transmitted when in Data Delay 0 (XDATDLY=00b) mode DXENA = 1 FSX ext P + 6 † Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ‡ 2P = 1/CLKG in ns. § C=CLKRX low pulse width = P D=CLKRX high pulse width = P |
|
Link URL |
| Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Liên kết đến bảng dữ liệu | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Vietnamese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
