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TMP320C2811PBKA bảng dữ liệu(PDF) 139 Page - Texas Instruments

tên linh kiện TMP320C2811PBKA
Giải thích chi tiết về linh kiện  TMS320R2811, TMS320R2812 Digital Signal Processors
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TMP320C2811PBKA bảng dữ liệu(HTML) 139 Page - Texas Instruments

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Electrical Specifications
139
June 2004
SPRS257
Table 6−47. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)†
NO
MASTER
SLAVE
UNIT
NO.
MIN
MAX
MIN
MAX
UNIT
M39
tsu(DRV-CKXH)
Setup time, DR valid before CLKX high
P-10
8P-10
ns
M40
th(CKXH-DRV)
Hold time, DR valid after CLKX high
P-10
8P-10
ns
M41
tsu(FXL-CKXH)
Setup time, FSX low before CLKX high
16P+10
ns
M42
tc(CKX)
Cycle time, CLKX
2P
16P
ns
Table 6−48. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)†
NO
PARAMETER
MASTER
SLAVE
UNIT
NO.
PARAMETER
MIN
MAX
MIN
MAX
UNIT
M34
th(CKXL-FXL)
Hold time, FSX low after CLKX low
P
ns
M35
td(FXL-CKXH)
Delay time, FSX low to CLKX high
2P
ns
M37
tdis(CKXL-DXHZ)
Disable time, DX high impedance following last data bit
from CLKX low
P + 6
7P+6
ns
M38
td(FXL-DXV)
Delay time, FSX low to DX valid
6
4P + 6
ns
† 2P = 1/CLKG
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. With
maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.5 MHz and P =13.3 ns.
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
CLKX
FSX
DX
DR
M35
M37
M40
M39
M38
M34
LSB
MSB
M41
M42
Figure 6−41. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0



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