TMP320C2811PBKA datasheet(131/147 Pages) TI

131 / 147 page

Electrical Specifications

131

June 2004

SPRS257

6.29.5

Detailed Description

6.29.5.1

Reference Voltage

The on-chip ADC has a built-in reference, which provides the reference voltages for the ADC. ADCVREFP

is set to 2.0 V and ADCVREFM is set to 1.0 V.

6.29.5.2

Analog Inputs

The on-chip ADC consists of 16 analog inputs, which are sampled either one at a time or two channels at a

time. These inputs are software-selectable.

6.29.5.3

Converter

The on-chip ADC uses a 12-bit four-stage pipeline architecture, which achieves a high sample rate with low

power consumption.

6.29.5.4

Conversion Modes

The conversion can be performed in two different conversion modes:

•

Sequential sampling mode (SMODE = 0)

•

Simultaneous sampling mode (SMODE = 1)

6.29.6

Sequential Sampling Mode (Single-Channel) (SMODE = 0)

In sequential sampling mode, the ADC can continuously convert input signals on any of the channels (Ax

to Bx). The ADC can start conversions on event triggers from the Event Managers (EVA/EVB), software

trigger, or from an external ADCSOC signal. If the SMODE bit is 0, the ADC will do conversions on the selected

channel on every Sample/Hold pulse. The conversion time and latency of the Result register update are

explained below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result register update.

The selected channels will be sampled at every falling edge of the Sample/Hold pulse. The Sample/Hold pulse

width can be programmed to be 1 ADC clock wide (minimum) or 16 ADC clocks wide (maximum).

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