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PM0056 bảng dữ liệu(PDF) 120 Page - STMicroelectronics

tên linh kiện PM0056
Giải thích chi tiết về linh kiện  This programming manual provides information
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
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PM0056 bảng dữ liệu(HTML) 120 Page - STMicroelectronics

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Core peripherals
PM0056
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DocID15491 Rev 5
4.3.2
Interrupt set-enable registers (NVIC_ISERx)
Address offset: 0x00 - 0x0B
Reset value: 0x0000 0000
Required privilege: Privileged
31
3029
28
27
26
25
24
23
22
21
20
19
18
17
16
SETENA[31:16]
rs
rs
rs
rs
rs
rs
rs
rs
rs
rs
rs
rs
rs
rs
rs
rs
15
14
13
12
11
10
9
8
76
54
3
21
0
SETENA[15:0]
rs
rs
rs
rs
rs
rs
rs
rs
rs
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rs
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rs
rs
Bits 31:0
SETENA[31:0]: Interrupt set-enable bits.
Write:
0: No effect
1: Enable interrupt
Read:
0: Interrupt disabled
1: Interrupt enabled.
See Table 41: Mapping of interrupts to the interrupt variables on page 119 for the
correspondence of interrupts to each register bit.
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an
interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending,
but the NVIC never activates the interrupt, regardless of its priority.



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