PM0056 datasheet(61/156 Pages) STMICROELECTRONICS

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PM0056

The Cortex-M3 instruction set

Note:

You might have to use the .W suffix to get the maximum offset range or to generate

addresses that are not word-aligned (see Instruction width selection on page 59).

Restrictions

Rd must be neither SP nor PC.

Condition flags

This instruction does not change the flags.

Examples

ADR R1, TextMessage; write address value of a location labelled as

; TextMessage to R1

3.4.2

LDR and STR, immediate offset

Load and store with immediate offset, pre-indexed immediate offset, or post-indexed

immediate offset.

Syntax

op{type}{cond} Rt, [Rn {, #offset}]; immediate offset

op{type}{cond} Rt, [Rn, #offset]!; pre-indexed

op{type}{cond} Rt, [Rn], #offset; post-indexed

opD{cond} Rt, Rt2, [Rn {, #offset}]; immediate offset, two words

opD{cond} Rt, Rt2, [Rn, #offset]!; pre-indexed, two words

opD{cond} Rt, Rt2, [Rn], #offset; post-indexed, two words

where:

•

‘op’ is either LDR (load register) or STR (store register)

•

‘type’ is one of the following:

B: Unsigned byte, zero extends to 32 bits on loads

SB: Signed byte, sign extends to 32 bits (LDR only)

H: Unsigned halfword, zero extends to 32 bits on loads

SH: Signed halfword, sign extends to 32 bits (LDR only)

—: Omit, for word

•

‘cond’ is an optional condition code (see Conditional execution on page 57)

•

‘Rt’ is the register to load or store

•

‘Rn’ is the register on which the memory address is based

•

‘offset’ is an offset from Rn. If offset is omitted, the address is the contents of Rn

•

‘Rt2’ is the additional register to load or store for two-word operations

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