PM0056 datasheet(96/156 Pages) STMICROELECTRONICS

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The Cortex-M3 instruction set

PM0056

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DocID15491 Rev 5

CMP

R0, #9

; Convert R0 hex value (0 to 15) into ASCII

; ('0'-'9', 'A'-'F')

ITE

; Next 2 instructions are conditional

ADDGT

R1, R0, #55

; Convert 0xA -> 'A'

ADDLE

R1, R0, #48

; Convert 0x0 -> '0'

; IT block with only one conditional instruction

ADDGT

R1, R1, #1

; Increment R1 conditionally

ITTEE

; Next 4 instructions are conditional

MOVEQ

R0, R1

; Conditional move

ADDEQ

R2, R2, #10

; Conditional add

ANDNE

R3, R3, #1

; Conditional AND

BNE.W

dloop

; Branch instruction can only be used in the last

; instruction of an IT block

; Next instruction is conditional

ADD

R0, R0, R1

; Syntax error: no condition code used in IT block

3.8.8

TBB and TBH

Table Branch Byte and Table Branch Halfword.

Syntax

TBB [Rn, Rm]

TBH [Rn, Rm, LSL #1]

where:

•

‘Rn’ is the register containing the address of the table of branch lengths.

If Rn is PC, then the address of the table is the address of the byte immediately

following the TBB or TBH instruction.

•

‘Rm’ is the index register. This contains an index into the table. For halfword tables,

LSL #1 doubles the value in Rm to form the right offset into the table.

Operation

These instructions cause a PC-relative forward branch using a table of single byte offsets for

TBB, or halfword offsets for TBH. Rn provides a pointer to the table, and Rm supplies an

index into the table. For TBB the branch offset is twice the unsigned value of the byte

returned from the table. and for TBH the branch offset is twice the unsigned value of the

halfword returned from the table. The branch occurs to the address at that offset from the

address of the byte immediately after the TBB or TBH instruction.

Restrictions

The restrictions are:

•

Rn must not be SP

•

Rm must not be SP and must not be PC

•

When any of these instructions is used inside an IT block, it must be the last instruction

of the IT block.

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