PM0056 datasheet(63/156 Pages) STMICROELECTRONICS

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PM0056

The Cortex-M3 instruction set

Condition flags

These instructions do not change the flags.

Examples

LDRR8, [R10]; loads R8 from the address in R10.

LDRNER2, [R5, #960]!; loads (conditionally) R2 from a word

; 960 bytes above the address in R5, and

; increments R5 by 960.

STRR2, [R9,#const-struc]; const-struc is an expression evaluating

; to a constant in the range 0-4095.

STRHR3, [R4], #4; Store R3 as halfword data into address in

; R4, then increment R4 by 4

LDRD R8, R9, [R3, #0x20]; Load R8 from a word 32 bytes above the

; address in R3, and load R9 from a word 36

; bytes above the address in R3

STRDR0, R1, [R8], #-16; Store R0 to address in R8, and store R1 to

; a word 4 bytes above the address in R8,

; and then decrement R8 by 16.

3.4.3

LDR and STR, register offset

Load and store with register offset.

Syntax

op{type}{cond} Rt, [Rn, Rm {, LSL #n}]

where:

•

‘op’ is either LDR (load register) or STR (store register)

•

‘type’ is one of the following:

B: Unsigned byte, zero extends to 32 bits on loads

SB: Signed byte, sign extends to 32 bits (LDR only)

H: Unsigned halfword, zero extends to 32 bits on loads

SH: Signed halfword, sign extends to 32 bits (LDR only)

—: Omit, for word

•

‘cond’ is an optional condition code (see Conditional execution on page 57)

•

‘Rt’ is the register to load or store

•

‘Rn’ is the register on which the memory address is based

•

‘Rm’ is a register containing a value to be used as the offset

•

‘LSL #n’ is an optional shift, with n in the range 0 to 3

Operation

LDR instructions load a register with a value from memory. STR instructions store a register

value into memory.

The memory address to load from or store to is at an offset from the register Rn. The offset is

specified by the register Rm and can be shifted left by up to 3 bits using LSL.

The value to load or store can be a byte, halfword, or word. For load instructions, bytes and

halfwords can either be signed or unsigned (see Address alignment on page 56).

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