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PM0056 bảng dữ liệu(PDF) 51 Page - STMicroelectronics |
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PM0056 bảng dữ liệu(HTML) 51 Page - STMicroelectronics |
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51 / 156 page  DocID15491 Rev 5 51/156 PM0056 The Cortex-M3 instruction set The CMSIS also provides a number of functions for accessing the special registers using MRS and MSR instructions (see Table 22). 3.3 About the instruction descriptions The following sections give more information about using the instructions: • Operands on page 51 • Restrictions when using PC or SP on page 52 • Flexible second operand on page 52 • Shift operations on page 53 • Address alignment on page 56 • PC-relative expressions on page 56 • Conditional execution on page 57 • Instruction width selection on page 59. 3.3.1 Operands An instruction operand can be an ARM register, a constant, or another instruction-specific parameter. Instructions act on the operands and often store the result in a destination register. When there is a destination register in the instruction, it is usually specified before the operands. Operands in some instructions are flexible in that they can either be a register or a constant (see Flexible second operand). Table 22. CMSIS intrinsic functions to access the special registers Special register Access CMSIS function PRIMASK Read uint32_t __get_PRIMASK (void) Write void __set_PRIMASK (uint32_t value) FAULTMASK Read uint32_t __get_FAULTMASK (void) Write void __set_FAULTMASK (uint32_t value) BASEPRI Read uint32_t __get_BASEPRI (void) Write void __set_BASEPRI (uint32_t value) CONTROL Read uint32_t __get_CONTROL (void) Write void __set_CONTROL (uint32_t value) MSP Read uint32_t __get_MSP (void) Write void __set_MSP (uint32_t TopOfMainStack) PSP Read uint32_t __get_PSP (void) Write void __set_PSP (uint32_t TopOfProcStack) |
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