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PM0056 bảng dữ liệu(PDF) 83 Page - STMicroelectronics

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PM0056 bảng dữ liệu(HTML) 83 Page - STMicroelectronics

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PM0056
The Cortex-M3 instruction set
3.6
Multiply and divide instructions
Table 28 shows the multiply and divide instructions.
3.6.1
MUL, MLA, and MLS
Multiply, multiply with accumulate, and multiply with subtract, using 32-bit operands, and
producing a 32-bit result.
Syntax
MUL{S}{cond} {Rd,} Rn, Rm ; Multiply
MLA{cond} Rd, Rn, Rm, Ra ; Multiply with accumulate
MLS{cond} Rd, Rn, Rm, Ra ; Multiply with subtract
where:
‘cond’ is an optional condition code (see Conditional execution on page 57)
‘S’ is an optional suffix. If S is specified, the condition code flags are updated on the
result of the operation (see Conditional execution on page 57).
‘Rd’ is the destination register. If Rd is omitted, the destination register is Rn
‘Rn’, ‘Rm’ are registers holding the values to be multiplied
‘Ra’ is a register holding the value to be added to or subtracted from
Table 28. Multiply and divide instructions
Mnemonic
Brief description
See
MLA
Multiply with accumulate, 32-bit result MUL, MLA, and MLS on page 83
MLS
Multiply and subtract, 32-bit result
MUL, MLA, and MLS on page 83
MUL
Multiply, 32-bit result
MUL, MLA, and MLS on page 83
SDIV
Signed divide
SDIV and UDIV on page 86
SMLAL
Signed multiply with accumulate
(32x32+64), 64-bit result
UMULL, UMLAL, SMULL, and SMLAL on
page 85
SMULL
Signed multiply (32x32), 64-bit result
UMULL, UMLAL, SMULL, and SMLAL on
page 85
UDIV
Unsigned divide
SDIV and UDIV on page 86
UMLAL
Unsigned multiply with accumulate
(32x32+64), 64-bit result
UMULL, UMLAL, SMULL, and SMLAL on
page 85
UMULL
Unsigned multiply (32x32), 64-bit
result
UMULL, UMLAL, SMULL, and SMLAL on
page 85



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