PM0056 datasheet(75/156 Pages) STMICROELECTRONICS

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PM0056

The Cortex-M3 instruction set

Multiword values do not have to use consecutive registers. Specific example 5: 96-bit

subtraction shows instructions that subtract a 96-bit integer contained in R9, R1, and R11

from another contained in R6, R2, and R8. The example stores the result in R6, R9, and R2.

Specific example 5: 96-bit subtraction

SUBSR6, R6, R9; subtract the least significant words

SBCSR9, R2, R1; subtract the middle words with carry

SBCR2, R8, R11; subtract the most significant words with carry

3.5.2

AND, ORR, EOR, BIC, and ORN

Logical AND, OR, exclusive OR, bit clear, and OR NOT.

Syntax

op{S}{cond} {Rd,} Rn, Operand2

where:

•

‘op’ is one of:

AND: Logical AND

ORR: Logical OR or bit set

EOR: Logical exclusive OR

BIC: Logical AND NOT or bit clear

ORN: Logical OR NOT

•

‘S’ is an optional suffix. If S is specified, the condition code flags are updated on the

result of the operation (see Conditional execution on page 57).

•

‘cond’ is an optional condition code (see Conditional execution on page 57)

•

‘Rd’ is the destination register

•

‘Rn’ is the register holding the first operand

•

‘Operand2’ is a flexible second operand (see Flexible second operand on page 52 for

details of the options).

Operation

The AND, EOR, and ORR instructions perform bitwise AND, exclusive OR, and OR

operations on the values in Rn and operand2.

The BIC instruction performs an AND operation on the bits in Rn with the complements of

the corresponding bits in the value of operand2.

The ORN instruction performs an OR operation on the bits in Rn with the complements of

the corresponding bits in the value of operand2.

Restrictions

Do not use either SP or PC.

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