PM0056 datasheet(93/156 Pages) STMICROELECTRONICS

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PM0056

The Cortex-M3 instruction set

Restrictions

The restrictions are:

•

Do not use PC in the BLX instruction

•

For BX and BLX, bit[0] of Rm must be 1 for correct execution but a branch occurs to the

target address created by changing bit[0] to 0

•

When any of these instructions is inside an IT block, it must be the last instruction of the

IT block.

Bcond is the only conditional instruction that is not required to be inside an IT block.

However, it has a longer branch range when it is inside an IT block.

Condition flags

These instructions do not change the flags.

Examples

loopA

; Branch to loopA

BLE

; Conditionally branch to label ng

B.W

target ; Branch to target within 16MB range

BEQ

target ; Conditionally branch to target

BEQ.W

target ; Conditionally branch to target within 1MB

funC

; Branch with link (Call) to function funC, return address

; stored in LR

; Return from function call

BXNE

; Conditionally branch to address stored in R0

BLX

; Branch with link and exchange (Call) to a address stored

; in R0

3.8.6

CBZ and CBNZ

Compare and branch on zero, compare and branch on non-zero.

Syntax

CBZ Rn, label

CBNZ Rn, label

where:

•

‘Rn’ is the register holding the operand.

•

‘label’ is the branch destination.

Operation

Use the CBZ or CBNZ instructions to avoid changing the condition code flags and to reduce

the number of instructions.

CBZ Rn, label does not change condition flags but is otherwise equivalent to:

CMP

Rn, #0

BEQ

label

CBNZ Rn, label does not change condition flags but is otherwise equivalent to:

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