PM0056 datasheet(116/156 Pages) STMICROELECTRONICS

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Core peripherals

PM0056

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DocID15491 Rev 5

4.2.9

MPU region attribute and size register (MPU_RASR)

Address offset: 0x10

Reset value: 0x0000 0000

Required privilege: Privileged

The MPU_RASR register defines the region size and memory attributes of the MPU region

specified by the MPU_RNR, and enables that region and any subregions.

MPU_RASR is accessible using word or halfword accesses:

•

The most significant halfword holds the region attributes

•

The least significant halfword holds the region size and the region and subregion

enable bits.

3029

Reserved

Res.

AP[2:0]

Reserved

TEX[2:0]

SRD[7:0]

Reserved

SIZE

ABLE

Bits 31:29

Reserved, forced by hardware to 0.

Bit 28

XN: Instruction access disable bit:

0: Instruction fetches enabled

1: Instruction fetches disabled.

Bit 27

Reserved, forced by hardware to 0.

Bits 26:24

AP[2:0]: Access permission

For information about access permission, see Section 4: Core peripherals

For the description of the encoding of the AP bits refer to

Table 37 on page 108.

Bits 23:22

Reserved, forced by hardware to 0.

Bits 21:19

TEX[2:0]: memory attribute

For the description of the encoding of the TEX bits refer to

Table 35 on page 107

Bit 18

S: Shareable memory attribute

For the description of the encoding of the S bits refer to

Table 35 on page 107

Bit 17

C: memory attribute

Bit 16

B: memory attribute

Bits 15:8

SRD: Subregion disable bits.

For each bit in this field:

0: corresponding sub-region is enabled

1: corresponding sub-region is disabled

See Subregions on page 110 for more information.

Region sizes of 128 bytes and less do not support subregions. When writing the attributes for

such a region, write the SRD field as 0x00.

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