ATF280F_14 datasheet(59/107 Pages) ATMEL

59 / 107 page

ATF280F [DATASHEET]

7750E

−AERO−05/12

Caution:

In parallel mode, the required interface for CHECK function is the same than for configuration

download. It means that for Mode 2, the IO743_A2_CS1 shall be used in parallel to the

IO655_CHECKN pin when starting the configuration download (dotted line in figure above).

Figure 6-5.

CHECK function in parallel mode 6

ATF280

FPGA

RESETn

Parallel

EEPROM

ADDR[19:0]

DATA[7:0]

/CE

/RESET_OE

READY

External Component to

start Configuration

Download

Reset EEPROM

counters

Start configuration

download

User applies a low logic level

before starting configuration

download on both signals

IOx_A[19:0]

IOx_D[7:0]

CON

IO303_INIT

IO259_LDC

IO265_HDC

IO655_CHECKN

Mode 6

DATA[15:8]

IOx_D[15:8] (1)

CLK

CCLK

Notes:

1. In parallel modes, ATF280F is capable to be accessed through a 16 bits wide data bus. Refer to Register

section for configuration.

Caution:

In parallel mode, the required interface for CHECK function is the same than for configuration

download. It means that for Mode 6, the IO743_A2_CS1 is used in the output address bus

IOx_A[19:0]. The pin IO655_CHECKN pin shall be used when starting the configuration download.

6.1.4

Behavior

The use of CHECK function is done by launching in Run lifephase a configuration download while IO655_CHECKN pin

is externally driven to a low logic level.

ATF280F bảng dữ liệu(PDF) 59 Page - ATMEL Corporation

ATF280F bảng dữ liệu(HTML) 59 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL