ATF280F_14 datasheet(9/107 Pages) ATMEL

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ATF280F [DATASHEET]

7750E

−AERO−05/12

IO655_CHECKN - Multiplexed General Purpose IO / Configuration Check

[CFG] CHECKN pin is used to enable the CHECK function when combined with a configuration download start.

[GPIO] General Purpose IO functionalities apply to this signal when used in IO mode.

IO225_OTSN - Multiplexed General Purpose IO / Tri-State Command

[CFG] OTSN pin is used to tri-state all the FPGA pins configured as user I/Os.

[GPIO] General Purpose IO functionalities apply to this signal when used in IO mode.

2.3

LVDS Interface

ILVDSx / ILVDSNx - LVDS Receiver Differential Pair (Input)

[LVDS] ILDVSx/ILVDSNx receiver is a pair of differential signals that comply with the LVDS standard.

OLVDSx / OLVDSNx - LVDS Driver Differential Pair (Output)

[LVDS] OLDVSx/OLVDSNx transmitter is a pair of differential signals that comply with the LVDS standard.

VREF - LVDS reference voltage

[LVDS] VREF is the reference voltage for LVDS transmission operations. Each LVDS cluster has dedicated VREF

source. It shall be accurately power supplied to 1.25V to comply with the LVDS standard.

2.4

Clocks Interface

IOx_FCKy - Multiplexed General Purpose IO / Fast Clock

[CLOCK] FCK function is used to provide high frequency clock to part of the design.

[GPIO] General Purpose IO functionalities apply to this signal when used in IO mode.

IOx_GCKy - Multiplexed General Purpose IO / Clock

[CLOCK] GCK function is used to provide clock signals over the entire surface of the FPGA.

[GPIO] General Purpose IO functionalities apply to this signal when used in IO mode.

IOx_GCKy_Az - Multiplexed General Purpose IO / Clock / Configuration Address

[CFG] A0:A23 are used to control external addressing of the memories during downloads.

[CLOCK] GCK function is used to provide clock signals over the entire surface of the FPGA.

[GPIO] General Purpose IO functionalities apply to this signal when used in IO mode.

IO720_GCK6_CSOUT - Multiplexed General Purpose IO / Clock / Configuration Select Output

[CFG] CSOUT is the configuration pin used to enable the downstream device in an FPGA cascade chain.

[CLOCK] GCK6 function is used to provide clock signals over the entire surface of the FPGA.

[GPIO] General Purpose IO functionalities apply to this signal when used in IO mode.

2.5

JTAG

TRST - Test Reset (pull-down input)

[JTAG] This asynchronous active low input resets the TAP when asserted.

This signal is meant for board testing purpose and shall be driven low in the final application.

TCK - Test Clock (pull-up input with Schmitt trigger)

[JTAG] This input is used to clock state information and test data into and out of the device during operation of the TAP.

ATF280F bảng dữ liệu(PDF) 9 Page - ATMEL Corporation