ATF280F_14 datasheet(14/107 Pages) ATMEL

14 / 107 page

ATF280F [DATASHEET]

7750E

−AERO−05/12

3.2.5

Configuration Self Internal Checker

The Configuration Self Internal Checker module is responsible of the integrity of the data during the Run lifephase.

Once the configuration SRAM is written with the appropriate data, the ATF280F FPGA is capable to check all its

effective configuration data and to notify the user in case of errors inside the configuration SRAM. This mechanism is

useful to detect SEU that occur on the configuration SRAM.

3.3

User I/O

Depending on the package selected, the ATF280F features up to 308 general purpose IO for end user application. Each

IO can be individually adjusted to the application needs thanks to its extensive configurability. All the IOs are cold

sparing, have PCI compliance capability…

Please refer to the General Purpose Interface section for detailed information on the User IOs.

3.4

LVDS I/O

The ATF280F provides a 200MHz LVDS interface with cold sparing feature. This interface can be used for high speed

communication between the FPGA and its peripherals in order to exchange large amount of data.

Please refer to the LVDS Interface section for detailed information on the LVDS IOs

3.5

Clock

Please refer to the Clock section for detailed information on clock system implemented on the ATF280F.

3.6

JTAG

The ATF280F implements a standard interface compliant with the IEEE 1149.1 JTAG specification. This interface can

be used for PCB testing using the JTAG boundary-scan capability.

ATF280F bảng dữ liệu(PDF) 14 Page - ATMEL Corporation