ATF280F_14 datasheet(21/107 Pages) ATMEL

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ATF280F [DATASHEET]

7750E

−AERO−05/12

IO720_GCK6_CSOUT, IO655_CHECKN and IO225_OTSN are configured in [CFG] function during

configuration download if the appropriate function is activated (respectively cascading mode, CHECK

function, Output Tri-State) (Refer to bitstream configuration for more details)

IOx_Dy pins ensure the data wide access in 8 or 16 bits. When parallel mode is set (mode 2 or 6),

I0x_D[1:7] are always configured as [CFG] function. By the way, IOx_D[8:15] are configured as [CFG]

function only if 16 bits access is configured (refer to Bitstream configuration for more details) else they

remain as [GPIO] function.

4.6

Run

4.6.1

Description

The Run lifephase is the operating state of the FPGA and is design dependent. It means that in this lifephase, the

loaded design runs and its own lifephases are taken into account.

4.6.2

Pin Function Availability

Table 4-6.

Pin Function during Run

Lifephase = Run

ATF280 Pin names

Nominal

OTS

CSIC

Free Run oscillator

RESET*

[CFG]

M0, M1, M2

[CFG]

IO303_INIT

[GPIO]

[CFG]

[GPIO]

CON

[CFG]

CCLK

[CFG]

IO713_D0

[GPIO]

IOx_Dy

[GPIO]

IO259_LDC

[GPIO]

IO265_HDC

[GPIO]

IO547_CS0

[GPIO]

IO743_A2_CS1

[GPIO]

IO720_GCK6_CSOUT

[GPIO]or[CLOC

[GPIO]or[CLOCK]

IOx_Az

[GPIO]

IOx_GCKy_Az

[GPIO]or[CLOC

[GPIO]or[CLOCK]

IO655_CHECKN

[GPIO]

IO225_OTSN

[GPIO]

[CFG]

[GPIO]

IOx

[GPIO]

IOx_GCKy

[GPIO]or[CLOC

[GPIO]or[CLOCK]

IOx_FCKy

[GPIO]or[CLOC

[GPIO]or[CLOCK]

Notes:

1. When using the Free Run Oscillator in mode 0 only (refer to Register section about CR13), the CCLK pin

is output as clock signal. The user shall take care of this at system level.

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