HCS12 datasheet(332/452 Pages) FREESCALE

332 / 452 page

S12CPUV2 Reference Manual, Rev. 4.0

332

Freescale Semiconductor

8.5.1.1 in_add, in_dat Registers

These registers contain the address and data from the previous external

bus cycle. Depending on how records are read and processed from the raw

capture information, it may be possible to simply read this information from

the raw capture data file when needed.

8.5.1.2 fetch_add, fetch_dat Registers

These registers buffer address and data for information that was fetched

before the queue was ready to advance.

8.5.1.3 st1_add, st1_dat Registers

These registers contain address and data for the first stage of the

reconstructed instruction queue.

8.5.1.4 st2_add, st2_dat Registers

These registers contain address and data for the final stage of the

reconstructed instruction queue. When the IPIPE1 and IPIPE0 signals

indicate that an instruction is starting to execute, the address and opcode

can be found in these registers.

8.5.2 Reconstruction Algorithm (for M68HC12)

This subsection describes in detail how to use IPIPE1 and IPIPE0 signals

and queue reconstruction registers to reconstruct the queue. An “is_full” flag

is used to indicate when the fetch_add and fetch_dat buffer registers

contain information. The use of the flag is explained more fully in

subsequent paragraphs.

Typically, the first few cycles of raw capture data are not useful because it

takes several cycles before an instruction propagates to the head of the

queue. During these first raw cycles, the only meaningful information

available are data movement signals. Information on the external address

and data buses during this setup time reflects the actions of instructions that

were fetched before data collection started.

In the special case of a reset, there is a 5-cycle sequence (VfPPP) during

which the reset vector is fetched and the instruction queue is filled, before

execution of the first instruction begins. Due to the timing of the switchover

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