HCS12 datasheet(328/452 Pages) FREESCALE

328 / 452 page

S12CPUV2 Reference Manual, Rev. 4.0

328

Freescale Semiconductor

8.3.8 SEV — Start Instruction on Even Address (Code 1:0)

The E cycle associated with this code is the first cycle of the instruction in

the even (high order) half of the word at the head of the instruction queue.

The queue treats the $18 prebyte for instructions on page 2 of the opcode

map as a special 1-byte, 1-cycle instruction, except that interrupts are not

recognized at the boundary between the prebyte and the rest of the

instruction.

8.3.9 SOD — Start Instruction on Odd Address (Code 1:1)

The E cycle associated with this code is the first cycle of the instruction in

the odd (low order) half of the word at the head of the instruction queue. The

queue treats the $18 prebyte for instructions on page 2 of the opcode map

as a special 1-byte, 1-cycle instruction, except that interrupts are not

recognized at the boundary between the prebyte and the rest of the

instruction.

8.4 Queue Reconstruction (for HCS12)

The raw signals required for queue reconstruction are the address bus

(ADDR), the data bus (DATA), the system clock (E), and the queue status

signals (IPIPE1 and IPIPE2). An ALD data movement implies a read;

therefore, it is not necessary to capture the R/W signal. An E clock cycle

begins at a falling edge of E. Addresses and execution status must be

captured at the rising E edge in the middle of the cycle. Data and

data-movement status must be captured at the falling edge of E at the end

of the cycle. These captures can then be organized into records with one

record per E clock cycle.

Implementation details depend on the type of MCU and the mode of

operation. For instance, the data bus can be eight bits or 16 bits wide, and

nonmultiplexed or multiplexed. In all cases, the externally reconstructed

queue must use 16-bit words. Demultiplexing and assembly of 8-bit data

into 16-bit words is done before program information enters the real queue,

so it must also be done for the external reconstruction.

An example:

Systems with an 8-bit data bus and a program stored in external memory

require two cycles for each program word fetch. MCU bus-control logic

freezes the CPU clocks long enough to do two 8-bit accesses rather than

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