HCS12 datasheet(50/452 Pages) FREESCALE

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S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

subroutine calls, branches, and jumps are considered to be elements of

program structure.

During design, great care is taken to assure that the mechanism that

increases instruction throughput during normal program execution does not

cause bottlenecks during changes of program flow, but internal queue

operation is largely transparent to the user. The following information is

provided to enhance subsequent descriptions of instruction execution.

4.4.1 Exceptions

Exceptions are events that require processing outside the normal flow of

instruction execution. CPU12 exceptions include five types of exceptions:

• Reset (including COP, clock monitor, and pin)

• Unimplemented opcode trap

• Software interrupt instruction

• X-bit interrupts

• I-bit interrupts

All exceptions use the same microcode, but the CPU follows different

execution paths for each type of exception.

CPU12 exception handling is designed to minimize the effect of queue

operation on context switching. Thus, an exception vector fetch is the first

part of exception processing, and fetches to refill the queue from the

address pointed to by the vector are interleaved with the stacking operations

that preserve context, so that program access time does not delay the

switch. Refer to Section 7. Exception Processing for detailed information.

4.4.2 Subroutines

The CPU12 can branch to (BSR), jump to (JSR), or call (CALL) subroutines.

BSR and JSR are used to access subroutines in the normal 64-Kbyte

address space. The CALL instruction is intended for use in MCUs with

expanded memory capability.

BSR uses relative addressing mode to generate the effective address of the

subroutine, while JSR can use various other addressing modes. Both

instructions calculate a return address, stack the address, then perform

three program word fetches to refill the queue.

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