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HCS12 bảng dữ liệu(PDF) 335 Page - Freescale Semiconductor, Inc

tên linh kiện HCS12
Giải thích chi tiết về linh kiện  HCS12 Microcontrollers
PDF  452 Pages
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nhà sản xuất  FREESCALE [Freescale Semiconductor, Inc]
Trang chủ  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

HCS12 bảng dữ liệu(HTML) 335 Page - Freescale Semiconductor, Inc

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S12CPUV2 Reference Manual, Rev. 4.0
Freescale Semiconductor
335
8.6 Instruction Tagging
The instruction queue and cycle-by-cycle CPU activity can be reconstructed
in real time or from trace history that was captured by a logic analyzer.
However, the reconstructed queue cannot be used to stop the CPU at a
specific instruction, because execution has already begun by the time an
operation is visible outside the MCU. A separate instruction tagging
mechanism is provided for this purpose.
Executing the BDM TAGGO command configures two MCU pins for
tagging. The TAGLO signal shares a pin with the LSTRB signal, and the
TAGHI signal shares the BKGD pin. Tagging information is latched on the
falling edge of ECLK, as shown in Figure 8-5.
Figure 8-5. Tag Input Timing
Table 8-2 shows the functions of the two independent tagging pins. The
presence of logic level 0 on either pin at the fall of ECLK tags (marks) the
associated byte of program information as it is read into the instruction
queue. Tagging is allowed in all modes. Tagging is disabled when BDM
becomes active.
Table 8-2. Tag Pin Function
TAGHI
TAGLO
Tag
1
1
No tag
1
0
Low byte
0
1
High byte
0
0
Both bytes
E CLOCK
LSTRB/TAGLO
BKGD/TAGHI
TAGS ARE APPLIED TO PROGRAM INFORMATION
CAPTURED ON THIS E CLOCK TRANSITION
LSTRB VALID
TAGLO
TAGHI
VALID
VALID



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