11 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision F (November 2013) to Revision G (September 2025)

Page

• Added the TMP411D-Q1 device throughout the document; updated the data sheet title.................................. 1

• Updated the look and feel of the document per the latest Texas Instruments and industry data sheet

standards............................................................................................................................................................ 1

• Added "Package Information" table to the Description section.......................................................................... 1

• Added "Device Comparison" table, "Device Nomenclature" figure and description........................................... 3

• Updated the "Conversion time" throughout the document................................................................................. 3

• Changed the Average and Shutdown currents throughout the document..........................................................3

• Added Pin Configurations and Functions section...............................................................................................5

• Added "Type" column to Pin Functions table......................................................................................................5

• Updated the maximum voltage ratings on D+/D- pins........................................................................................6

• Updated the maximum voltage rating on pins 4, 6, 7, 8..................................................................................... 6

• Updated the maximum voltage rating on V+ pin................................................................................................ 6

• Updated Human body model (HBM) and Charged device model (CDM) Electrostatic discharge for TMP411-

Q1....................................................................................................................................................................... 6

• Added DGK and DDF packages Thermal Information section........................................................................... 6

• Updated the typo and moved "TA = 15°C to 85°C, V+ = 3.3V" from Remote temperature error to Local

temperature error................................................................................................................................................7

• Added "TDIODE = –40°C to 150°C" condition to temperature error power supply sensitivity.............................. 7

• Added "Conversion time" for the New chip in Electrical Characteristics table....................................................7

• Updated the typo for Hysteresis typical value from 500mV to 170mV................................................................7

• Added "Logic input current" for the New chip in Electrical Characteristics table................................................ 7

• Added "Output low voltage" for the New chip in Electrical Characteristics table................................................7

• Added "High-level output leakage current" for the New chip in Electrical Characteristics table.........................7

• Updated the typo and added 6mA min to “ALERT or THERM2 output low sink current”................................... 7

• Added "Quiescent current" for the New chip and all test conditions in the Electrical Characteristics table........7

• Removed limitation on Undervoltage lockout..................................................................................................... 7

• Added "Power-on-reset threshold" for the new chip in the Electrical Characteristics table................................7

• Added Brownout detect value in the Electrical Characteristics table..................................................................7

• Changed t(SUDAT) in High-Speed Mode from 10ns to 20ns........................................................................... 11

• Added "Typical Characteristics (TMP411-Q1)" graphs for the New chip..........................................................12

• Added an overview in the Detailed Description section....................................................................................19

• Updated the Basic Connections figure in the Overview section....................................................................... 19

• Added Functional Block Diagram section.........................................................................................................20

• Added Feature Description section and relocated feature information to this section......................................20

• Added "12-bit Q4 parameters and Bit values" tables along with its C code..................................................... 20

• Updated the Undervoltage Lockout section due to Undervoltage Lockout voltage removal by POR in the

New chip...........................................................................................................................................................23

• Added Device Functional Modes section......................................................................................................... 24

• Clarified the Shutdown Mode (SD) section to match actual silicon behavior................................................... 24

• Changed the terminology "Master" to "Controller" and "Slave" to "Target" throughout the document..............25

• Added Timing Diagrams to the Specifications section..................................................................................... 25

• Added "TMP411-Q1 and TMP411D-Q1 Device Address Options" table.......................................................... 28

• Changed REGISTER INFORMATION section to Register Maps section and centralized register information in

this section........................................................................................................................................................32

• Updated the Status Register section due to Undervoltage lockout voltage removal by POR in the New chip.33

• Added "Application Information" section...........................................................................................................40

• Added D+ waveform in the Design Requirements section............................................................................... 41

• Updated Detailed Design Procedure section....................................................................................................42

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TMP411-Q1, TMP411D-Q1

SBOS527G – DECEMBER 2010 – REVISED SEPTEMBER 2025

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Product Folder Links: TMP411-Q1 TMP411D-Q1