TMP411D datasheet(28/60 Pages) TI2

28 / 60 page

Measured

Temperature

THERM Limit and ALERT High Limit

ALERT Low Limit and THERM Limit Hysteresis

THERM

ALERT

SMBus ALERT

Read

Time

Read

Figure 7-9. SMBus Alert Timing Diagram

7.5.4 Serial Bus Address

To communicate with the TMP411-Q1 and TMP411D-Q1, the controller must first address target devices through

a target address byte. The target address byte consists of seven address bits and a direction bit that indicates

whether the operation is read or write. The addresses of the TMP411A-Q1 and TMP411DA-Q1, and the

TMP411D-Q1 and TMP411DD-Q1 devices are 4Ch (1001100b).

Table 7-5. TMP411-Q1 and TMP411D-Q1 Device Address Options

DEVICE NAME

PART NUMBER

I2C BINARY ADDRESS

I2C HEX ADDRESS

DEFAULT LOCAL/

REMOTE HIGH

TEMPERATURE LIMIT

TMP411-Q1

(DGK package)

TMP411AQDGKRQ1

100 1100b

4Ch

+85°C

TMP411BQDGKRQ1

100 1101b

4Dh

+85°C

TMP411CQDGKRQ1

100 1110b

4Eh

+85°C

TMP411DQDGKRQ1

100 1100b

4Ch

+110°C

TMP411D-Q1

(DDF package)

TMP411DAQDDFRQ1

100 1100b

4Ch

+85°C

TMP411DBQDDFRQ1

100 1101b

4Dh

+85°C

TMP411DCQDDFRQ1

100 1110b

4Eh

+85°C

TMP411DDQDDFRQ1

100 1100b

4Ch

+110°C

7.5.5 Read/Write Operations

To access a particular register on the TMP411-Q1 and TMP411D-Q1, the appropriate value must be written to

the Pointer Register. With the read and write bit low, the value for the Pointer Register is the first byte transferred

after the target address byte. Every write operation to the TMP411-Q1 and TMP411D-Q1 requires a value for the

Pointer Register, as shown in Figure 7-5.

When reading from the TMP411-Q1 and TMP411D-Q1 devices, the last value stored in the Pointer Register by

a write operation is used to determine which register is read by a read operation. To change the register pointer

for a read operation, a new value must be written to the Pointer Register. This transaction is accomplished

by issuing a target address byte with the R/W bit low, followed by the Pointer Register byte. No additional

data is required. The controller then generates a START condition and sends the target address byte with the

R/W bit high to initiate the read command. See Figure 7-6 for details of this sequence. Continually sending

the Pointer Register bytes is not necessary if repeated reads from the same register are desired, because the

TMP411-Q1 and TMP411D-Q1 devices retain the Pointer Register value until the value is changed by the next

write operation. Note that the MSB sends the register bytes first, followed by the LSB.

7.5.6 Time-Out Function

When bit 7 of the Consecutive Alert Register is set high, the TMP411-Q1 and TMP411D-Q1 time-out function is

enabled. The TMP411-Q1 and TMP411D-Q1 reset the serial interface if either SCL or SDA is held low for 30ms

TMP411-Q1, TMP411D-Q1

SBOS527G – DECEMBER 2010 – REVISED SEPTEMBER 2025

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