TMP411D datasheet(25/60 Pages) TI2

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7.5 Programming

7.5.1 Serial Interface

The TMP411-Q1 and TMP411D-Q1 devices operate only as a target device on either the two-wire bus or the

SMBus. Connections to either bus are made through the open-drain I/O lines, SDA and SCL. The SDA and SCL

pins feature integrated spike suppression filters and Schmitt triggers to minimize the effects of input spikes and

bus noise. The TMP411-Q1 and TMP411D-Q1 support the transmission protocol for fast (1kHz to 400kHz) and

high-speed (1kHz to 3.4MHz) modes. All data bytes are transmitted with the MSB first.

7.5.2 Bus Overview

The TMP411-Q1 and TMP411D-Q1 devices are SMBus interface-compatible. In the SMBus protocol, the device

that initiates the transfer is called a controller, and the devices controlled by the controller are targets. The bus

must be controlled by a controller device that generates the serial clock (SCL), controls the bus access, and

generates the START and STOP conditions.

To address a specific device, a START condition is initiated. START is indicated by pulling the data line (SDA)

from a high to a low logic level while SCL is high. All targets on the bus shift are in the target address byte, with

the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the target being

addressed responds to the controller by generating an Acknowledge and pulling SDA low.

Data transfer is then initiated and sent over eight clock pulses, followed by an Acknowledge bit. During data

transfer, the SDA line must remain stable while SCL is high, because any change in SDA while SCL is high is

interpreted as a control signal.

Once all data has been transferred, the controller generates a STOP condition. STOP is indicated by pulling the

SDA line from low to high while the SCL line is high.

7.5.3 Timing Diagrams

The TMP411-Q and TMP411D-Q1 devices are two-wire and SMBus-compatible. Figure 7-5 to Figure 7-8

describe the various operations on the TMP411-Q1 and TMP411D-Q1. Bus definitions are given as follows:

Bus Idle: Both SDA and SCL lines remain high.

Start Data Transfer: A change in the state of the SDA line, from high to low (while the SCL line is high), defines

a START condition. A START condition initiates each data transfer.

Stop Data Transfer: A change in the state of the SDA line from low to high (while the SCL line is high) defines a

STOP condition. A STOP or repeated START condition terminates each data transfer.

Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and

is determined by the controller device. The receiver acknowledges the data transfer.

Acknowledge: Each receiving device (when addressed) is required to generate an Acknowledge bit. A device

that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the

SDA line is stable low during the high period of the Acknowledge clock pulse. Setup and hold times must

be taken into account. On a controller receive, the controller signals data transfer termination by generating a

not-acknowledge bit transmitted by the controller.

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TMP411-Q1, TMP411D-Q1

SBOS527G – DECEMBER 2010 – REVISED SEPTEMBER 2025

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