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(typical) between a START and STOP condition. If the TMP411-Q1 and TMP411D-Q1 devices are holding the

bus low, the devices release the bus and wait for a START condition. Maintaining a communication speed of

at least 1kHz for the SCL operating frequency is necessary to avoid activating the timeout function. The default

state of the timeout function is enabled (bit 7 = high).

7.5.7 High-Speed Mode

For the two-wire bus to operate at frequencies above 400kHz, the controller device must issue a high-speed

mode (Hs-mode) controller code (00001XXX) as the first byte after a START condition to switch the bus to

high-speed operation. The TMP411-Q1 and TMP411D-Q1 devices do not acknowledge this byte, but switch the

input filters on SDA and SCL lines, switch the output filter on SDA to operate in Hs-mode, which allows transfers

at up to 3.4MHz. After the Hs-mode controller code is issued, the controller transmits a two-wire target address

to initiate a data transfer operation. The bus operates in Hs-mode until a STOP condition occurs on the bus. The

TMP411-Q1 and TMP411D-Q1 devices switch the input and output filter after receiving the STOP condition.

7.5.8 General-Call Reset

The TMP411-Q1 and TMP411D-Q1 devices support a reset through the two-wire general-call address 00h (0000

0000b). The TMP411-Q1 and TMP411D-Q1 devices acknowledge the general-call address and respond to the

second byte. If the second byte is 06h (0000 0110b), the TMP411-Q1 and TMP411D-Q1 execute a software

reset. This software reset restores the power-on-reset state to all TMP411-Q1 and TMP411D-Q1 registers,

aborts any conversion in progress, and clears the ALERT and THERM pins. The TMP411-Q1 and TMP411D-Q1

do not respond to other values in the second byte.

7.5.9 Software Reset

The TMP411-Q1 and TMP411D-Q1 reset by writing any value to Pointer Register FCh. This restores the

power-on-reset state to all of the TMP411-Q1 and TMP411D-Q1 registers, aborts any conversion in process, and

clears the ALERT and THERM pins.

7.5.10 SMBUS Alert Function

The TMP411-Q1 and TMP411D-Q1 support the SMBus alert function. When pin 6 is configured as an alert

output, the ALERT pin of the TMP411-Q1 and TMP411D-Q1 can be connected as an SMBus alert signal.

When a controller detects an alert condition on the ALERT line, the controller sends an SMBus alert command

(0001 1001) on the bus. If the ALERT pin of the TMP411-Q1 and TMP411D-Q1 devices is active, the device

acknowledges the SMBus alert command and returns the target address on the SDA line. The eighth bit (LSB) of

the target address byte indicates whether the temperature exceeding one of the temperature high limit settings

or falling below one of the temperature low limit settings caused the alert condition. The bit is high if the

temperature is greater than one of the temperature high limit settings; the bit is low if the temperature is less than

or equal to one of the temperature low limit settings. See Figure 7-9 for details of this sequence.

If multiple devices on the bus respond to the SMBus alert command, arbitration during the target address portion

of the SMBus alert command determines which device clears the alert status. If the TMP411-Q1 and TMP411D-

Q1 win the arbitration, the ALERT pin becomes inactive at the completion of the SMBus alert command. If the

TMP411-Q1 and TMP411D-Q1 devices lose the arbitration, the ALERT pin remains active.

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TMP411-Q1, TMP411D-Q1

SBOS527G – DECEMBER 2010 – REVISED SEPTEMBER 2025

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