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TMP411D bảng dữ liệu(PDF) 27 Page - Texas Instruments |
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TMP411D bảng dữ liệu(HTML) 27 Page - Texas Instruments |
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27 / 60 page ![]() Frame 1 Two Wire Device Address Byte Frame 2 Pointer Register Byte Host Device Device 9 SCL 1 9 1 1 Start By ACK By ACK By SDA 0 0 1 1 0 0 P6 P7 P5 P4 P3 P2 P1 P0 (1) W / R Frame 3 Two Wire Device Address Byte Frame 4 Data Byte 1 Read Register Host Device Host 9 SCL 1 9 1 1 Start By ACK By ACK By SDA 0 0 1 1 0 0 D6 D7 D5 D4 D3 D2 D1 D0 (1) W / R (Continued) (Continued) From Device SDA (Continued) SCL (Continued) Stop By Host NACK By Host From Device 1 9 D7 D6 D5 D4 D3 D2 D1 D0 Frame 5 Data Byte 2 Read Register (2) A. Target address 1001 100 (TMP411A-Q1/TMP411DA-Q1 and TMP411D-Q1/TMP411DD-Q1) shown. Target address changes for TMP411B-Q1/TMP411DB-Q1 and TMP411C-Q1/TMP411DC-Q1. See the Ordering Information table for more details. B. The host must leave SDA high to terminate a two−byte read operation. Figure 7-7. Two-Wire Timing Diagram for Two-Byte Read Format Start By Host ACK By Device From Device NACK By Host Stop By Host 1 9 1 9 SDA SCL ALERT 0 0 0 1 1 0 0 R/W 1 0 0 1 Status Frame 2 Device Address Byte Frame 1 SMBus ALERT Response Address Byte 0 0 (1) 1 A. Target address 1001 100 (TMP411A-Q1/TMP411DA-Q1 and TMP411D-Q1/TMP411DD-Q1) shown. Target address changes for TMP411B-Q1/TMP411DB-Q1 and TMP411C-Q1/TMP411DC-Q1. See the Ordering Information table for more details. Figure 7-8. Timing Diagram for SMBus ALERT www.ti.com TMP411-Q1, TMP411D-Q1 SBOS527G – DECEMBER 2010 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: TMP411-Q1 TMP411D-Q1 |
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