L9679E datasheet(113/127 Pages) STMICROELECTRONICS

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13.10

Arming interface

All electrical characteristics are valid for the following conditions unless otherwise noted:

-40 °C ≤ Tamb ≤ +105 °C

VSAT_ON(max) ≤ VSAT ≤ VSAT(max)

VCCx(min) ≤ VCCx ≤ VCCx(max)

VCC = 3.3 V or 5 V

Table 35. Arming interface – DC specifications

Symbol

Parameter

Comments / Conditions

Min

Typ

Max

Unit

VIH_FENx

FENx high level input voltage

VIL_FENx

FENx low level input voltage

0.8

IPD_FENx

FEN1/FEN2 pull down current

FENx = VCC

µA

IPD_FENL

FENL passive pull down

FENL = VCC

100

160

VOH_FENL

FENL high level output voltage

ILOAD = -800 µA

VCC-0.5

VCC

VOL_FENL

FENL low level output voltage

ILOAD = 2.0 mA

0.4

13.11

Analog-to-digital converter

All electrical characteristics are valid for the following conditions unless otherwise noted:

-40 °C ≤ Tamb ≤ +105 °C

VSAT_ON(max) ≤ VSAT ≤ 17.5 V

Table 36. Analog-to-digital converter

Symbol

Parameter

Comments / Conditions

Min

Typ

Max

Unit

VADC_RANGE ADC input voltage range

Design info

0.1

2.5

VADC_REF

ADC reference voltage

-1.5%

2.5

+1.5%

ADC_RES

ADC resolution(1)

Design info

bit

DNL

Differential non linearity error (DNL)

Separation between adjacent levels, measured bit

to bit of actual and an ideal output step. No missing

codes

-1

LSB

INL

Integral non linearity error (INL)

Maximum difference between the actual analog

value at the transition between 2 adjacent steps and

its ideal value

-3

LSB

EQUANT

Quantization error

Design info

-0.5

0.5

LSB

TotErr

Total error

Includes INL, DNL, ADC reference voltage tolerance

and quantization error

-15

+15

LSB

TotErr_0v1

ADC total error for 0.1 V input voltage

-5

LSB

TotErr_2v4

ADC total error for 2.4V input voltage

-15

+15

LSB

RLSB_1

Reproducibility: conversion result variation

for constant input signal

1x sampling measurements. Guaranteed by design

-6

LSB

RLSB_4

Reproducibility: conversion result variation

for constant input signal

4x sampling measurements. Guaranteed by design

-3

LSB

RLSB_8

Reproducibility: conversion result variation

for constant input signal

8x sampling measurements. Guaranteed by design

-2.5

2.5

LSB

Pre-ADC

Pre-ADC settling time

4.81

µs

T_SC

Single conversion time

2.25

µs

L9679E

Electrical characteristics

DS12485 - Rev 8

page 113/127

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