L9679E datasheet(17/127 Pages) STMICROELECTRONICS

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SPI interface

The L9679E has many user-selectable features controlled through serial communications by the integrated

microcontroller. The device features two SPI interfaces: one global SPI and one remote sensor SPI. The global

SPI interface provides general configuration, control and status functions for the device, while the remote sensor

SPI provides dedicated communication of the remote sensor data and status registers to the microcontroller.

6.1

SPI protocol

Each SPI interface (global and remote sensor) uses its own dedicated set of 4 I/O pins: CS_G, SCLK_G,

MOSI_G and MISO_G for Global SPI; CS_RS, SCLK_RS, MOSI_RS and MISO_RS for remote sensor SPI. Both

of the SPI interfaces use the same protocol described here below (the suffix “_X” used in the SPI pin names

below is intended to stand for either “_G” or “_RS” depending on the specific SPI interface considered)

The IC SPI interface is composed by an input shift register, an output shift register and four control signals.

MOSI_X is the data input to the input shift register. MISO_X is the data output from the output shift register.

SCLK_X is the clock input used to shift data into the input shift register or out from the output one while CS_X is

the active low chip select input.

All SPI communications are executed in exact 32-bit increments. The general format of the 32-bit transmission for

the SPI interface is shown in Table 5. SPI MOSI_X frame layout and Table 6. SPI MISO_X frame layout

The data sent to the IC (i.e. MOSI_X) consists of a target read register ID (RID), a target write register ID (WID),

write data parity (WPAR) and 16 bits of data (WRITE). WRITE data is the data to be written to the target write

data parity (RPAR) and 20 bits of data (READ). READ data will be the contents of the target read register as

indicated by the RID bits. The parity bits WPAR and RPAR cover all the 32 bits of the MOSI and MISO frames,

respectively. Odd parity type is used.

Table 5. SPI MOSI_X frame layout

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

RID[6:0]

WID[6:0]

WRITE[15:0]

Table 6. SPI MISO_X frame layout

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

GSW[10:0]

READ[19:0]

Communications are controlled through CS_X, enabling and disabling communication. When CS_X is at high

logic, all SPI communication I/O is tri-stated and no data is accepted. When CS_X is low, data is latched on the

rising edge of SCLK_X and data is shifted on the falling edge. The MOSI_X pin receives serial data from the

master with MSB first. Likewise for MISO_X, data is read MSB first, LSB last.

The L9679E features a data validation method through the SCLK_X input to keep transmissions with not exactly

32 bits from being written to the device. The SCLK_X input counts the number of received clocks and should the

clock counter exceed or count fewer than 32 clocks, the received message is discarded and a SPI_FLT bit is

flagged in the Global Status Word (GSW). The SPI_FLT bit is also set in case of parity error detected on the

MOSI_X frame. Any attempt to access a register with forbidden access mode (read or write) does not lead to

changes to the internal registers, but the SPI_FLT bit is not set in this case.

6.2

Global SPI register map

The Global SPI interface consists of several 32-bit registers which allow the configuration, control and status of

the IC as well as special manufacturing test modes. The register definition is defined by the read register ID (RID)

and the write register ID (WID) as shown in Table 7. Global SPI register map. The Global ID bit (GID) is used to

extend the available register addresses, but it is shared between RID and WID; only RID and WID with the same

GID value can be addressed within the same SPI word. The operating states here below show in which states the

SPI command is processed.

L9679E

SPI interface

DS12485 - Rev 8

page 17/127

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