TMS470MF06607 datasheet(12/65 Pages) TI2

12 / 65 page

TMS470MF06607

SPNS157C

– JANUARY 2012

www.ti.com

Table 2-7. Flash Memory Banks and Sectors (continued)

SECTOR

MEMORY ARRAYS (OR

SEGMENT

LOW ADDRESS

HIGH ADDRESS

NO.

BANKS)

16k

0x0008_0000

0x0008_3FFF

BANK 1(1)

(128K Bytes)

16k

0x0008_4000

0x0008_7FFF

16k

0x0008_8000

0x0008_BFFF

16k

0x0008_C000

0x0008_FFFF

64k

0x0009_0000

0x0009_FFFF

(1)

Bank 1 can be used as either EEPROM emulation space or as program space.

2.2

Terminal Functions

The terminal functions table (Table 2-8) identifies the pin names, the associated pin numbers, input

voltage, output voltage, whether the pin has any internal pullup/pulldown resistors and a functional pin

description.

Table 2-8. Terminal Functions

TERMINAL

INPUT

OUTPUT

VOLTAGE(1)

IPU/IPD(4)

DESCRIPTION

100

CURRENT(3)

NAME

(2)

HIGH-END TIMER (HET)

HET[0]

HET[1]

HET[2]

HET[3]

Timer input capture or output compare. The

HET[4]

HET[15:0] applicable pins can be programmed as

HET[5]

general-purpose input/output (GIO) pins. All are

HET[6]

high-resolution pins.

HET[7]

The high-resolution (HR) SHARE feature allows even

Adaptive

HR pins to share the next higher odd HR pin

HET[8]

Programmable

3.3-V I/O

impedance 4

structures. This HR sharing is independent of whether

IPD (100

µA)

HET[9]

or not the odd pin is available externally. If an odd pin

is available externally and shared, then the odd pin

HET[10]

can only be used as a general-purpose I/O.

HET[11]

NOTE: HET[24] and HET[25] channels are muxed

HET[12]

with TDO/TDI pins. During debug, their respective

HET[13]

input buffers will reflect the state of TDI and TDO.

HET[14]

HET[15]

HET[24]

HET[25]

CAN CONTROLLER 1 (DCAN1)

CAN1STX

Adaptive

DCAN1 transmit pin or GIO pin.

Programmable

3.3-V I/O

impedance 4

CAN1SRX

DCAN1 receive pin or GIO pin.

IPU (100

µA)

CAN CONTROLLER 2 (DCAN2)

CAN2STX

Adaptive

DCAN2 transmit pin or GIO pin

Programmable

3.3-V I/O

impedance 4

CAN2SRX

DCAN2 receive pin or GIO pin

IPU (100

µA)

(1)

PWR = power, GND = ground, REF = reference voltage, NC = no connect

(2)

All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.

(3)

The TMS470M device utilizes adaptive impedance 4 mA buffers that default to the adaptive impedance mode of operation. As a

fail-safe, the adaptive impedance features of the buffer may be disabled and revert the buffer to a standard buffer mode.

(4)

IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are inactive on input pins when PORRST is asserted)

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