TMS470MF06607 datasheet(28/65 Pages) TI2

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TMS470MF06607

SPNS157C

– JANUARY 2012

www.ti.com

3.11 Built-In Self Test (BIST) Features

3.11.1 STC/LBIST

The TMS470M family supports a logic built-in self test (LBIST or CPUBIST) of the M3 CPU.

LBIST testing can be performed in two modes of operation:

•

Full Execution. In this mode, the full suite of test patterns is run without interruption. This test is

started via CPU control and is well suited for use at device start up.

•

Cyclic Execution. During cyclic execution, a small percentage of time will be dedicated to running a

subset of the self-test (STC Intervals). This mode is well suited for executing on a periodic basis to

minimize the bandwidth use. After all STC intervals are executed, all test patterns will have been run.

NOTE

1. The application will need to disable peripherals and or interrupts to avoid missing

interrupts.

2. No debugger interaction is possible with the CPU during self test. This includes access to

memory and registers since access is through the CPU.

The default value of the LBIST clock prescaler (STCDIV) is divide-by-1; however, the maximum STC CLK

is limited by the current consumption and supply capability of the Vreg. For specified maximum STC clock

rates for specified operating frequencies, see Table 3-12.

Table 3-12. Maximum STC Clock Frequencies vs HCLK(1)

HCLK

STC DIVIDER

STC CLOCK

FREQUENCY (MHz)

(STC_DIV+1)

FREQUENCY (MHz)

(1)

The maximum LBIST STC clock frequency is limited to 40MHz.

A single LBIST interval is 158 STC CLK cycles in duration, excluding clock transition timing of 20 cycles.

This device has 550 total intervals.

Figure 3-3. CPU BIST Intervals vs Coverage

Device Configuration

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